Patents Assigned to Western Digital
  • Selective rebuild of interrupted devices in data storage device arrays
    Patent number: 11853163
    Abstract: Systems and methods for selective rebuild of interrupted data storage devices in storage arrays are described. A controller determines an operating interruption of a data storage device in a redundant array of independent disks (RAID) configuration. In response to the interruption, the controller determines a last block time value for the last successfully stored RAID block in the interrupted storage device and one or more incomplete RAID stripes that the interrupted storage device did not complete. The controller then selectively rebuilds the incomplete RAID stripes from the other storage devices in the RAID configuration.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kushal Hosmani
  • Key value data storage device with tiers
    Patent number: 11853563
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Avraham, Alexander Bazarsky, Ran Zamir
  • Hardware accelerator circuits for near storage compute systems
    Patent number: 11853239
    Abstract: An apparatus is provided that includes a memory system that includes a memory controller coupled to a storage device capable of streaming data at a first data rate. The memory controller is configured to read a first amount of input data from the storage device at an input data rate equals the first data rate, and provide the first amount of input data at the input data rate to a hardware circuit. The hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate. The hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the storage device, a memory buffer, and the hardware circuit.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mikael Mortensen, Grant Mackey
  • Adaptive multi-stream classification for data storage systems
    Patent number: 11853595
    Abstract: A stream set classification process may be implemented to classify streams opened by a host device on a data storage device. The data storage device may internally classify the streams into different stream classifications using a set of performance metrics. Stream classifications that cause the data storage device to show the greatest gains when compared with a set of baseline performance metrics for the data storage device and/or when compared with other stream classifications, may be selected by the data storage device and/or the host device for subsequent write operations.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Matar Krizhak, Stella Achtenberg, Hadas Oshinsky
  • Systems and methods with variable size super blocks in zoned namespace devices
    Patent number: 11853203
    Abstract: During a garbage collection process of a data storage device, superblocks may be filled with dummy data, which may decrease device performance. Embodiments described herein provide systems, methods, and computer readable media for varying a size of a superblock to reduce or eliminate dummy data in a data storage device including a plurality of superblocks. Each of the plurality of superblocks including a plurality of die blocks.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avinash Muthya Narahari, Sampath Kumar Raja Murthy, Aakar Deora
  • Controlled system management based on storage device thermal load
    Patent number: 11853612
    Abstract: A storage system includes two or more data storage devices and a controller coupled to the two or more data storage devices. Each data storage device of the two or more data storage devices includes zoned namespace (ZNS) architecture. The controller is configured to collect thermal statistics for each data storage device of the two or more data storage devices, analyze the collected thermal statistics, and designate a zone by selecting one or more dies within at least one data storage device of the two or more data storage devices based on the analyzed collected thermal statistics. The data storage device includes a memory device having a plurality of dies and a controller coupled to the memory device. The controller is configured to collect thermal statistics for each die of the plurality of dies, analyze the collected statistics, and allocate one or more dies to form a zone.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avichay Haim Hodes, Judah Gamliel Hahn, Alexander Bazarsky
  • ACTIVE TIME-BASED COMMAND PRIORITIZATION IN DATA STORAGE DEVICES
    Publication number: 20230409236
    Abstract: Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan MUTHIAH, Judah Gamliel HAHN, Rotem SELA
  • Data Storage Device and Method for Host Multi-Command Queue Grouping Based on Write-Size Alignment in a Multi-Queue-Depth Environment
    Publication number: 20230409234
    Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
  • Key Value Data Storage Device With Tiers
    Publication number: 20230409212
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: David AVRAHAM, Alexander BAZARSKY, Ran ZAMIR
  • APPARATUS AND METHODS FOR PROGRAMMING MEMORY CELLS
    Publication number: 20230410910
    Abstract: An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 21, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ming Wang, Liang Li, Ke Zhang
  • SEMICONDUCTOR WAFER THINNED BY HORIZONTAL STEALTH LASING
    Publication number: 20230411169
    Abstract: A method includes the step of thinning a semiconductor wafer by a horizontal stealth lasing process, and semiconductor wafers, dies and devices formed thereby. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by supporting an active surface of the wafer on a rotating chuck, and focusing a horizontally-oriented laser in multiple cycles at different radii within the rotating wafer. Upon completion of the multiple cycles, a portion of the wafer substrate may be removed, leaving the wafer thinned to its final thickness. Thereafter, a vertical stealth lasing process may be performed to cut individual semicondcutor dies from the thinned wafer.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yi Wu, Junrong Yan, Zhonghua Qian, Keming Zhou, Kailei Zhang
  • Spin Torque Oscillator with Enhanced Spin Polarizer
    Publication number: 20230410841
    Abstract: The present disclosure generally relates to a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield of the magnetic recording head. The spintronic device comprises a multilayer spacer layer comprising a Cu layer in contact with a spin torque layer and a spin transparent texture layer disposed on the Cu layer, the spin transparent texture layer comprising AgSn or AgZn. A multilayer notch comprising a CoFe layer is disposed over the spin transparent texture layer of the multilayer spacer layer and a Heusler alloy layer is disposed on the CoFe layer, the Heusler alloy layer comprising CoMnGe, CoFeGe, or CoFeMnGe. The multilayer spacer layer and the multilayer notch result in the spintronic device having a high spin polarization and a reduced critical current.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: James Mac FREITAG, Susumu OKAMURA, Christian KAISER
  • Data Storage Device With Weak Bits Handling
    Publication number: 20230409237
    Abstract: A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to the second wordline, re-read and store the first data from the first wordline in a second location during the programming, compare the read first data and the re-read first data, and mark one or more bits of the first wordline that are different based on the comparing. The marked one or more bits are used as soft bits in future read and decode operations.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventor: Refael Ben RUBI
  • Laser Cutting With Electron Removal
    Publication number: 20230411179
    Abstract: The present disclosure generally relates to ensuring a plasma plume or cloud that forms during a laser cutting process does not lead to undesired re-deposition of material onto the substrate. At least one electrode is biased to draw the electrons of the plasma plume or cloud towards the electrode and away from the substrate. A vacuum port and/or a blower may be strategically located to ensure proper gas flow away from the substrate and hence, directing of the electrons away from the substrate. In so doing, material re-deposition is less likely to occur.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cong ZHANG, Hope CHIU, Yiqin HUANG, Guocheng ZHONG, Weiting JIANG, Dongpeng XUE
  • Spin Torque Oscillator with Multilayer Seed for Improved Performance and Reliability
    Publication number: 20230410840
    Abstract: The present disclosure generally relates to a magnetic recording device having a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield at a media facing surface. The spintronic device comprises a spin torque layer (STL) and a multilayer seed layer disposed in contact with the STL. The spintronic device may further comprise a field generation layer disposed between the trailing shield and the STL. The multilayer seed layer comprises an optional high etch rate layer, a heat dissipation layer comprising Ru disposed in contact with the optional high etch rate layer, and a cooling layer comprising Cr disposed in contact with the heat dissipation layer and the main pole. The high etch rate layer comprises Cu and has a high etch rate to improve the shape of the spintronic device during the manufacturing process.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: James Mac FREITAG, Yongchul AHN, Susumu OKAMURA, Christian KAISER
  • Regenerative Braking For Tape Drive
    Publication number: 20230410844
    Abstract: The present disclosure generally relates to a tape drive having a regenerative braking system. The tape drive comprises a first reel; a first spindle coupled to the first reel; a first motor coupled to the first spindle, wherein the first motor is configured to rotate the first spindle; a second reel; a second spindle coupled to the second reel; a second motor coupled to the second spindle, wherein the second motor is configured to rotate the second spindle; and a regenerative braking circuit coupled to the first motor and the second motor, wherein during a braking of the motors, the regenerative braking circuit and the motors convert a mechanical energy of the motors to electrical energy for a power storage mechanism, thereby providing resistance to the rotation of the spindles.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventor: Erhard SCHRECK
  • SEMICONDUCTOR DEVICE INCLUDING EMBEDDED MEMORY DIES AND METHOD OF MAKING SAME
    Publication number: 20230411340
    Abstract: A semiconductor device includes a signal carrier medium such as a PCB substrate having first and second opposed surfaces and a cavity formed in the second surface. A first set of one or more semiconductor dies are mounted on the first surface, and a second set of one or more semiconductor dies are mounted within the cavity. The first and/or second sets of semiconductor dies may be memory dies.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 21, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lee Kong Yu, Yoong Tatt Chin, Kim Lee Bock, Paramjeet Gill, Wei Chiat Teng, Chong Un Tan
  • Flash Translation Layer Mapping For Large Capacity Data Storage Devices
    Publication number: 20230409475
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Vered KELNER, Marina FRID, Igor GENSHAFT
  • Storage System and Method for Implementation of Symmetric Tree Models for Read Threshold Calibration
    Publication number: 20230410869
    Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Alexander Bazarsky, David Avraham, Nika Yanuka, Idan Alrod
  • Key Value Data Storage Device With Improved Utilization For Short Key Value Pairs
    Publication number: 20230409213
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, store the received KV pair data in an intermediate storage location, match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, where the matching is based on a utilization parameter of a storage container of the memory device, aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location, and program the aggregated KV pair data to the memory device.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: David AVRAHAM, Alexander BAZARSKY, Ran ZAMIR