Abstract: A storage system stores data in a primary block and a copy of the data in a secondary block. Parity bits are stored with the data and the copy of the data. A header with logical block information is stored with the copy of the data in the secondary block. The data in the primary block is not stored with a header, which allows more parity bits to be stored with the data in the primary block. This provides more robust error protection for the data stored in the primary block and reduces the need to rely upon the copy of the data in the secondary block.

Abstract: The present invention provides a coal-based solid waste transport and filling integrated machine mining system, comprising a filling hydraulic support (6) and a coal winning machine (7), said filling hydraulic support (6) comprises a hydraulic top plate and a base (601), said hydraulic top plate comprises a hinged front top beam (602) and a rear top beam (603), with a front probe beam (604) attached to front end of said front top beam (602) and a telescopic slide rod (1) connected to rear end of said rear top beam (603), a double transport and single filling non-stop equipment is fixed on the telescopic slide rod (1). The apparatus and method of the present invention weaken the impact of groundwater pollution on mine production and mine ecology, bring good economic and environmental benefits to the mine and promoting safe and green coal mining.

Abstract: A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, determine an entropy value of the received KV pair data, select an error correction code (ECC) code rate based on the determined entropy value, and program the KV pair data to a codeword (CW). The KV pair data includes a key and a value. The programming includes encoding the KV pair data using the selected ECC code rate. The controller is further configured to aggregate a portion of another KV pair data and the KV pair data and program the aggregated KV pair data to the CW using a selected ECC code rate.

Abstract: A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlayer disposed on the BiSb layer. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer each comprise at least one of a covalently bonded amorphous material, a tetragonal (001) material, a tetragonal (110) material, a body-centered cubic (bcc) (100) material, a face-centered cubic (fcc) (100) material, a textured bcc (100) material, a textured fcc (100) material, a textured (100) material, or an amorphous metallic material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the BiSb layer and enhance uniformity of the BiSb layer while further promoting the (012) orientation of the BiSb layer.

Abstract: A data storage device comprises a first memory, a second memory, and a controller. The first memory has a faster access time than the second memory. The controller is configured to store host-initialization code in the first memory, store a copy of the host-initialization code in the second memory, determine that the copy of the host-initialization code should be designated as the main version of the host-initialization code, and relocate the copy of the host-initialization code to the first memory, which makes the copy of the host-initialization code the main version of the host-initialization code that is accessed to boot-up the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.

Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The substrate includes a top layer and a bottom layer. The first stack of memory dies is electrically coupled to the top layer of the substrate and includes a controller and a first number of memory dies. The second stack of memory dies is electrically coupled to the top layer of the substrate and includes a second number of memory dies greater than the first number of memory dies. An upper surface of the first stack of memory dies and an upper surface of the second stack of memory dies are substantially coplanar.

Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.

Abstract: Disclosed herein is a data storage device. A data port transmits data between a host computer system and the data storage device. A non-volatile storage medium stores encrypted user content data and a cryptography engine uses a cryptographic key to decrypt the encrypted user content data stored on the storage medium in response to a request from the host computer system. An access controller receives a request from a manager device to initialize the data storage device. The controller generates the cryptographic key, generates a manager key configured to provide manager access for the manager device and provide access to the cryptographic key, and stores, on a data store, authorization data indicative of the manager key and accessible based on a private key stored on the manager device.

Abstract: A thermal surrogate device is configured to replace a data storage device within a server or other multiple data storage device system. The thermal surrogate device has a housing that has a form factor identical to the data storage device. The housing has a cavity along a length, and a sensor fixture is positioned within the housing. An airflow sensor is attached to the sensor fixture and configured to measure an airflow through the housing. The housing is configured to be installed within a slot for a data storage device in a multiple memory system.

Abstract: Methods and apparatus are provided for arbitrating access to, and usage of, various device resources of a data storage device (DSD) configured for Machine Learning with Low-Power. The data storage device may include a TinyML controller with an artificial intelligence (AI) accelerator integrated with a data storage controller on a system-on-a-chip (SoC). The device resources may be, e.g., storage resources such as random access memory (RAM) devices, non-volatile memory (NVM) arrays, and latches formed on NVM dies of the NVM arrays. The resource arbitration may be based, for example, on parameters pertaining to ML operations performed by an ML controller that includes the AI accelerator, such as a turnaround time of an ML epoch or a stage-wise execution time. The resource arbitration is configured to provide for the efficient interleaving of the ML/AI operations performed by the ML controller and data storage operations performed by the data storage controller.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a hint calibration operation is needed, select a first hint mode out of a plurality of hint modes, generate one or more hints based on a selected hint mode, and select a hint mode based on one or more of a performance, quality of service, and power consumption of the data storage device. The controller is further configured to iterate through the plurality of hint modes during the hint calibration operation and operate based on the selected hint mode until the controller determines that another hint calibration operation is needed.

Abstract: Aspects of a storage device are provided which apply advanced thermal throttling in response to temperature changes based on multiple thermal power states for different types of cells, such as SLCs and MLCs. Initially, a controller determines that a temperature of the memory meets a thermal throttling threshold of a plurality of thermal throttling thresholds. Subsequently, the controller transitions into a thermal power state of a plurality of thermal power states when the temperature meets the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state. The controller then determines that the temperature of the memory has reached a thermal equilibrium in the thermal power state based on the thermal mitigation configuration. Storage device performance is thus improved through advanced thermal throttling without compromising data integrity.

Abstract: Multi-signal vias for use with differential pair signals in electronic devices. The electronic devices include a printed circuit board having a first side and a second side opposite the first side, a first conductive trace on the first side of the substrate and a second conductive trace on the first side of the substrate. The printed circuit board also includes a shared via, which includes a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are separated by a non-conductive portion. The first conducive trace is coupled to the first conductive portion of the shared via and the second conductive trace is coupled to the second conductive portion of the shared via.

Abstract: Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuating mechanism comprising one or more heads, and configured to position the one or more heads proximate to disk surfaces of the one or more disks; and one or more processing devices. The one or more processing devices are configured to: determine a first burst value based on an averaged value of a first set of one or more bursts; determine a second burst value based on an averaged value of a second set of one or more bursts; generate a position error signal (PES) based on the determined first burst value and the determined second burst value; and control a position of at least one head among the one or more heads based on the PES.

Abstract: An apparatus for detecting the presence of assembly related defects on a semiconductor device including an edge ring having a resistance value and including one or more layers configured to at least partially cover the semiconductor device in a first direction. The one or more layers are divided into a first section and a second section. Each layer of the one or more layers are in electrical communication with one another. The resistance value of the edge ring is at a first resistance value associated with the first and second sections being intact. At least one of the first section and second section is configured to break in response to an assembly related defect, and the resistance value of the edge ring is configured to change from the first resistance value to a second resistance value in response to at least one of the first and second sections being broken.

Abstract: A storage device is provided that performs constant biasing in priority blocks, such as OTP memory blocks (fuse ROM) and flash memory blocks having a threshold number of P/E cycles. The storage device includes an OTP memory, a flash memory, and a controller. The OTP memory includes a block having a word line and a plurality of cells coupled to the word line. The flash memory includes another block having a word line and a plurality of cells coupled to this word line. The controller is configured to apply a constant bias to the word line of the OTP memory block and, in some cases to the word line of the flash memory block, between execution of host commands. As a result, lower bit error rates due to wider Vt margins may occur while system power may be saved through selective application of constant biasing.

Abstract: A testing apparatus for Devices Under Test (DUTs) includes at least one intake damper and at least one exhaust damper. At least one fan moves recirculated fluid and exterior fluid across one or more DUTs inside the testing apparatus. In one aspect, the testing apparatus includes a door to provide access to a chamber and the door includes at least one channel. At least a portion of the fluid flows through the at least one channel of the door. In another aspect, the door is configured to provide access to a chamber from the front of the chamber and the fluid is moved in a direction across the one or more DUTs substantially from the front of the chamber towards a rear of the chamber.