Patents Assigned to Western Digital
  • SEMICONDUCTOR DEVICE INCLUDING SELECT DIES OF KNOWN THICKNESSES
    Publication number: 20230395438
    Abstract: A semiconductor device includes a die stack having dies selected into the stack based on their thicknesses. After the dies are formed on a wafer and thinned, a metrology tool is used to determine the thicknesses of the dies in the wafer. These thicknesses are stored in a known thickness die (KTD) map, along with other information such as their standard and average deviations and their classification into a binning class. In one example, dies which have been classified into bin 1 (having an optimal thickness) are selected to provide a high capacity highly reliable semiconductor device. In a further example, dies of different bins are mixed and matched to provide a uniform, highly controlled overall die stack height.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nagesh Vodrahalli, Chih Yang Li, Xuyi Yang, Cong Zhang
  • Data Storage Device and Method for Host Buffer Management
    Publication number: 20230393738
    Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Partial speed changes to improve in-order transfer
    Patent number: 11838033
    Abstract: The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky, David Avraham
  • Distribution of logical-to-physical address entries across multiple memory areas
    Patent number: 11836354
    Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jameer Mulani, Kapil Sundrani, Anindya Rai
  • Magnetoresistive memory device including a plurality of reference layers
    Patent number: 11839162
    Abstract: Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 5, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alan Kalitsov, Derek Stewart, Bhagwati Prasad, Goran Mihajlovic
  • Automatic prediction timers adaptation
    Patent number: 11836384
    Abstract: Data storage devices function by communication between a controller and a memory device over a data bus. The memory device can, at times, be busy. Attempting to communicate with the memory device while the memory device is busy causes delays. Holding back communications when the memory device is not busy causes avoidable delays. Correctly predicting the timing of when the memory device is available will reduce delays. An adaptive prediction timer is used that increases the time between communications if a status check of the memory device returns a busy indication, and decreases the time between communications if the status check returns a not busy indication.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Gadi Vishne, Michal Silbermintz, Danny Berler
  • Storage system and method for data placement in zoned storage
    Patent number: 11836374
    Abstract: A storage system uses blocks of memory that are sized larger than a size of a zone. This means that the storage system stores multiple zones in a given block. Storing zones with different zone properties in a given block can be problematic, so the storage system obtains zone property information for each zone and stores zones with similar zone properties in a given block.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Asher Druck
  • Data storage device with data verification circuitry
    Patent number: 11836035
    Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Linnen, Aashish Sangoi, Kirubakaran Periyannan, Judah Gamliel Hahn
  • Advanced ultra low power error correcting code encoders and decoders
    Patent number: 11838032
    Abstract: Advanced ultra-low power error correcting codes are generated using soft quantization and lattice interpolation based on clock and Syndrome Weight. Reinforcement learning may be used to generate threshold values for flipping bits for low density parity check Ultra-Low Power error correction codes. The threshold values can be generated offline and downloaded to a storage device or generated while the storage device is in use.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ofir Pele, Stella Achtenberg, Ran Zamir, Omer Fainzilber
  • Flip-chip package with reduced underfill area
    Patent number: 11837476
    Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 5, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
  • Reference-guided genome sequencing
    Patent number: 11837330
    Abstract: Methods and systems for processing a plurality of sample reads for genome sequencing include, for each sample read of the plurality of sample reads, comparing substring sequences from the sample read to reference sequences representing different portions of a reference genome. One or more reference sequences are identified that match one or more of the compared substring sequences, and a probabilistic location within the reference genome is determined for the sample read based on the one or more identified reference sequences. The reference genome is partitioned for reference-aligned genome sequencing based on the determined probabilistic locations of the respective sample reads.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Justin Kinney
  • Dual slc/qlc programming and resource releasing
    Patent number: 11837277
    Abstract: The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Karin Inbar, Shay Benisty
  • In-line data identification on network
    Patent number: 11838222
    Abstract: A programmable network switch includes at least one pipeline including a packet parser configured to parse packets, and a plurality of ports for communication with network devices including a plurality of Data Storage Devices (DSDs). A packet comprising a write command is received to store data in a DSD of the plurality of DSDs, and an identifier generated for the data is compared to a plurality of identifiers generated for data stored in the plurality of DSDs. It is determined whether to send the write command to store the data to the DSD based on whether the generated identifier matches an identifier of the plurality of identifiers. In one aspect, the data to be stored for the write command is extracted from the packet using a pipeline of the programmable network switch, and at least a portion of the extracted data is used to generate the identifier for the data.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Pietro Bressana, Dejan Vucinic
  • Micro solder joint and stencil aperture design
    Patent number: 11839031
    Abstract: Micro solder joint and stencil design. In one embodiment, a stencil for depositing solder on a printed circuit board (PCB) includes a plurality of stencil apertures, a first stencil aperture of the plurality of apertures having an aperture wall defining an aperture perimeter. The aperture wall is configured to not extend beyond an outer edge of a PCB pad provided on the printed circuit board, the aperture wall is also configured to not extend beyond an outer edge of a terminal of a surface mount component, and the first stencil aperture is configured to receive solder paste to form a non-convex solder joint between the PCB pad and the terminal.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Patrick Burke, Ibrahym bin Ahmad, Fakhrozi Bin Che Ani, Mohamad Solehin Bin Mohamed Sunar, Peir Ming Sing, Hari Kiran Raavi
  • Data storage device having dual actuators and method for data egress throttling during emergency power off retract (EPOR)
    Patent number: 11837264
    Abstract: A data storage device comprises a lead actuator that actuates a first read-write head over a first disk and a support actuator that actuates a second read-write head over a second disk. A spindle motor rotates the first and second disks. In response to an emergency power off (EPO) event, a processing device retracts and parks the actuators using an internal supply voltage generated from a back electromotive force (BEMF) voltage of the spindle motor, and egresses data from a volatile to a non-volatile semiconductor memory. Egress is throttled before the actuators are retracted and parked when the internal supply voltage falls to or below a first egress throttling threshold voltage. Egress is throttled after the actuators are retracted and parked when the internal supply voltage falls to or below a second egress throttling threshold voltage.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Brian Johnson, Jaesoo Byoun, Gaku Ikedo, Hideaki Ito, Naoyuki Kagami, Hiroki Watanabe
  • Data Storage Device and Method for Lane Detection and Configuration
    Publication number: 20230385210
    Abstract: A data storage device and method for lane detection and configuration are provided. In one embodiment, a data storage device is provided comprising a memory, an interface, and a controller. The controller is configured to detect whether a cable coupled with the interface is providing a first channel configuration signal that indicates that the cable is in a first cable orientation or a second channel configuration signal that indicates that the cable is in a second cable orientation. In response to detecting that the cable is not providing either the first or the second channel configuration signal, the controller uses a default lane configuration to communicate with the host via the cable. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Anil Kumar Kolar Narayanappa, Yogesh Tayal
  • Storage System and Method for Data Placement in Zoned Storage
    Publication number: 20230384966
    Abstract: A storage system uses blocks of memory that are sized larger than a size of a zone. This means that the storage system stores multiple zones in a given block. Storing zones with different one properties in a given block can be problematic, so the storage system obtains zone property information for each zone and stores zones with similar zone properties in a given block.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Asher Druck
  • Data Storage Device and Method for Lane Selection Based on Thermal Conditions
    Publication number: 20230385211
    Abstract: A data storage device and method for lane selection based on thermal conditions are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that action is needed to control a thermal state of the data storage device; and in response to determining that action is needed to control the thermal state of the data storage device, send a request to a host to reduce a number of lanes the host uses to communicate with the data storage device, wherein reducing the number of lanes reduces an amount of heat generated by the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Yogesh Tayal, Anil Kumar Kolar Narayanappa
  • Tape Assemblies Having Flangeless Reel Configurations and Single Flange Reel Configurations For Magnetic Recording Devices
    Publication number: 20230386517
    Abstract: The present disclosure generally relate to tape assembly implementations for magnetic recording devices, such as tape embedded drives (TEDs). In one or more embodiments, a first reel and a second reel are mounted at stationary positions. One or more of the first reel and/or the second reel includes a hub mounted to a spindle, and a single flange extending relative to the hub. In one or more embodiments, one or more of a first reel and/or a second reel each includes a flangeless hub mounted to a spindle.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Erhard SCHRECK, Robert SMITH
  • Storage System and Method for Early Command Cancelation
    Publication number: 20230384976
    Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty