Abstract: Apparatuses, systems, and methods for low latency parity for a memory device include a controller configured to accumulate, in a memory buffer, combined parity data for a plurality of regions of memory of a memory device in response to write operations for the plurality of regions of memory. The controller is configured to perform a recovery operation for a region of memory in response to determining that a latency setting for the region satisfies a latency threshold. The controller is configured to service a read request for data from the region based on a recovery operation to satisfy the latency setting.

Abstract: A data storage device having an FTL configured to award to some pending memory operations a higher priority compared to the priority given to those operations by a default scheduling scheme. Such awards of higher priority may be based on a policy directed, e.g., at maximizing the effective data throughput, balancing the data throughput and the input/output bus throughput, or other performance objective. In response to awards of higher priority, a power-management circuit of the data storage device may dynamically route a constrained power supply such that the storage dies corresponding to the higher-priority operations preferentially receive power allocation in the next time interval(s). The remainder of the power budget (if any) in those time intervals may be allocated in accordance with the default scheduling scheme.

Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.

Abstract: A data storage device and method for progressive fading for video surveillance systems are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to store a plurality of digital video frames in the memory over time; and create free space in the memory by deleting some of the plurality of digital video frames across a plurality of subsets of digital video frames, wherein fewer digital video frames are deleted from a subset stored more recently in time than from a subset stored less recently in time. Other embodiments are provided.

Abstract: Variable Capacity Zone Namespace (ZNS) Flash Storage Data Path. In one example, a data storage device including an electronic processor that, when executing a variable capacity scheme, is configured to determine whether a special indication regarding a particular zone in a ZNS is received, delay an association of a final flash block with the particular zone, receive and stage host data for the particular zone in a staging area, receive a zone close request, compact the host data with other host data for storage in other zones into second host data, and move the second host data to the final flash block that is associated with the particular zone and the other zones. The compaction of the host data with the other host data into the second host data reduces or eliminates padding in the final flash block, and consequently, reduces overhead in the data storage device.

Abstract: A data storage device includes a non-volatile memory device having a number of memory dies. The data storage device further includes a controller. The controller is configured to poll each of the memory dies at a first predetermined rate for a thermal status bit and determine whether the thermal status bit of at least one memory die of the number of memory dies is an active thermal status bit activated. The controller is further configured to reduce the operating performance of the at least one memory die in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit.

Abstract: A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.

Abstract: Disclosed herein are systems and devices for detecting molecules. In some embodiments, a system for detecting molecules comprises an amplifier and a nanopore unit, wherein the nanopore unit comprises a nanopore, a sense electrode, a counter electrode, and a shield situated between the sense electrode and the counter electrode and coupled to an output of the amplifier. The shield may be recessed from a hole in the nanopore. A system or device may include an array of nanopore units that may share some components, such as a read amplifier, a digitizer, drive circuitry, control logic, and/or a multiplexer.

Abstract: Various illustrative aspects are directed to a data storage device, comprising: one or more disks; a write mechanism configured to write data to disk surfaces of the one or more disks; and one or more processing devices, which are configured to: encode, based on a distributed sector encoding scheme, data into a plurality of logic blocks of data, wherein the logic blocks of data comprise the data to be written being interleaved across a plurality of sectors; assign at least some of the logic blocks to a plurality of containers of two or more container sizes, the container sizes comprising a relatively larger container size and a relatively smaller container size; and output a write signal to the write mechanism to write the logic blocks in accordance with the assigning of the at least some of the logic blocks to the plurality of containers.

Abstract: A storage device and methods of operation are disclosed. The device comprises a controller configured to execute a read command, a write command, a first vendor specific command, and a second vendor specific command, and further comprises a persistent memory and a non-persistent memory. When executing the first vendor specific command, the device begins operation in a first vendor specific mode. In this mode, the device stores write data in the non-persistent memory and does not immediately commit the write data to persistent memory. When executing the second vendor specific command, the device begins operation in a second vendor specific mode. In this mode, the device immediately commits write data to persistent memory. The first vendor specific mode is ideal when power supplies are healthy and redundant, while the second vendor specific mode is ideal when power supplies are not redundant and/or healthy.

Abstract: A data storage device whose controller is configured to apply a hash function to a logical address specified in a received host request to obtain a first portion of the corresponding physical address (e.g., the channel number or channel and die numbers). This feature of the controller enables the L2P table stored in the DRAM associated with the controller to have physical-address entries that contain therein only complementary second portions of the physical addresses, but not the first portions. Such shorter physical-address entries in the L2P table enable a corresponding beneficial reduction in the size of the DRAM and can further be leveraged to have optimized and aligned access to the L2P table in the DRAM.

Abstract: A multi-actuator hard disk drive includes a lower actuator with a corresponding voice coil motor assembly (VCMA) including a magnet coupled with a first magnet housing plate, a coaxial upper actuator with a corresponding VCMA including a magnet coupled with a second magnet housing plate, and a central support plate mechanically fastened to an enclosure base, at one or more locations, and positioned between the first magnet housing plate of the first VCMA and the second magnet housing plate of the second VCMA. Thereby, the pivot and VCM tilt and the coil torsion modes of the direct plant transfer function are minimized and the peak-to-peak gain in the coil torsion mode of the coupled plant transfer function is reduced.

Abstract: A slider may include a first side-edge surface, a second side-edge surface, and an air-bearing surface (ABS) comprising: a first side cavity adjacent to the first side-edge surface, and a first island side blocker situated at a mouth of the first side cavity, wherein: a first outer surface of the first island side blocker forms a portion of the first side-edge surface, a second outer surface of the first island side blocker is recessed from the first side-edge surface, a first side opening is situated on a leading side of the first island side blocker, and a second side opening is situated on a trailing side of the first island side blocker.

Abstract: A data storage device and method for providing an adaptive data path are disclosed. In one embodiment, a data storage device is in communication with a host comprising a first processor (e.g., a graphics processing unit (GPU)), a second processor (e.g., a central processing unit (CPU)), and a queue. The data storage device chooses a data path to use to communicate with the queue based on whether the queue is associated with the first processor or with the second processor. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Embodiments of serial neural network configuration and processing via a common serial bus are disclosed. In some embodiments, the input data and source identification data is sent to nodes of the neural network serially. The nodes can determine whether the source identification data matches with an address for the node. If the address matches, the node can store the input data in its register for further processing. In some embodiments, the serial neural network engine can include a common serial bus that can broadcast data across multiple processor chips or cores.

Abstract: A data storage device and method for auto-peeling of surveillance video content to increase archival storage is provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that available storage space in the memory is less than a threshold; in response to determining that the available storage space in the memory is less than the threshold: read a video file from the memory; and re-encode the video file to decrease a size of the video file, wherein re-encoding the video file increases available storage space in the memory without deleting the video file. Other embodiments are provided.

Abstract: A data storage device includes a non-volatile memory device having one or more memory dies and each of the memory dies include a plurality of input-output (I/O) lines. The data storage device further includes a controller. The controller is configured to receive an instruction to enter a low-power operating mode. Entering the low-power operating mode includes removing power from the one or more memory dies, providing an output signal toggling between a logic high and a logic low at a predetermined frequency to the plurality of I/O lines for a predetermined period of time, and operating in the low-power operating mode upon the expiration of the predetermined period of time.

Abstract: The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.