Abstract: A method is provided to fabricate a mask ROM device via a medium current implanter. For fabricating the mask ROM device, first, formation of an array of MOS transistors on a semiconductor substrate is achieved. Each of the MOS transistors includes a gate oxide film, a gate electrode, a source region and a drain region. After the formation of the array of transistors, a USG layer, a BPSG layer, metal electrodes and a passivation layer are sequentially formed. After an order from client, an etching back process is performed to remove selected portions of the passivation layer to form openings in accordance with a ROM code. The selected portions are located over the selected gate electrodes respectively. The portions of the BPSG layer within the openings are successively etched until the remained BPSG layer is in a predetermined thickness. Finally, ROM code ions are implanted into the substrate via a medium current implanter through the openings.

Abstract: A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions.

Abstract: An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate. The split gate flash memory is fabricated using a process comprising the steps of: (a) forming a floating gate with an overlaying poly oxide layer on a substrate, wherein the floating gate is etched to have a reentrant angle such that its width generally increases with a distance from the substrate; (b) forming a CVD nitride spacer on the floating gate using a CVD nitride deposition, then anisotropic etching the CVD nitride to form a nitride spacer adjacent to the floating gate; (c) forming a control gate on the floating gate wherein the control gate and the floating gate are separated by the poly oxide and the nitride spacer; and (d) forming a source and drain in the substrate using a source and drain implantation.

Abstract: A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer.

Abstract: A method for manufacturing an inductor with resonant frequency and Q value increased in semiconductor process can reduce substrate coupling effect, because (an) air layer(s) is/are formed just under a spiral metal layer which functions as an inductor. In addition, part of the substrate material still remains around the air layer(s), which can be used as a support for the spiral metal layer. Therefore, a problem causing the above-mentioned spiral metal layer to collapse will never occur.

Abstract: A non-intrusive method for in-situ measurement of etching chamber and optionally etch rate inside a plasma etching chamber is disclosed for use in the fabrication of semiconductor devices. The method includes the step of selecting at least one plasma species as a probe which can be F, CF.sub.2, or CO, then measuring the emission intensity at a predetermined wavelength corresponding to the plasma species so selected. Preferably, the emission intensity is measured at wavelength of 686 nm (corresponding to the transition of F from 3s.sup.3 P.sub.3 to 3p.sup.4 P.sub.3), 269 or 239 nm, corresponding to the transitions from A.sup.1 B.sub.1 (v'=0) to X.sup.1 A.sub.1 (v"=0) and from A.sup.1 B.sub.1 (v'=9) to X.sup.1 A.sub.1 (v"=0) for CF.sub.2, respectively, and 693 or 505 nm, corresponding to the transitions from d.sup.3 .PI.(v'=2) to a.sup.3 .PI.(v"=2) and from d.sup.3 .PI.(v'=7) to a.sup.3 .PI.(v"=2) for CO, respectively.

Abstract: A method and apparatus for noise burst detection in a signal processor is provided. The method and apparatus is based on the zero-crossing rate (ZCR) of the received signal, which is defined as the number of times the magnitude of the received signal becomes zero during a specific counting period, to determine whether the received signal is a noise or a normal signal. The received signal is sampled at a specified sampling rate. Whether the signal waveform undergoes a zero-crossing is determined by comparing the polarity of the current sampled magnitude with that of the previous one. If the polarities are different, it indicates that the signal waveform has undergone a zero-crossing during the current sampling period; otherwise, it indicates that the signal waveform has not undergone a zero-crossing. The count of zero-crossing during each counting period is compared with a preset threshold value.

Abstract: An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

Abstract: A segmented SCR ESD protection circuit for discharging an external electrostatic stress on a semiconductor integrated circuit is formed over a semiconductor substrate. The protection circuit includes an SCR device and a number of resistors. The SCR device is separated into a plurality of SCR segments for suppressing the occurrence of the secondary breakdown. Each of the resistors is connected to one of the SCR segments. The resistors can be in the form of parasitic resistances of the SCR device or in the form of additional electronic components formed on the semiconductor substrate.

Abstract: An integrated circuit which is switchable between a line driver function and a bidirectional transceiver function is provided. The integrated circuit comprises a first buffer, a second buffer and a logic control function. The first buffer has a first input terminal, a first output terminal, and a first control terminal which receives a first control signal. The second buffer has a second input terminal coupled to the first output terminal, has a second output terminal coupled to the first input terminal and has a second control terminal which receives a second control signal. The logic control function generates the first and second control signals responsive to a selection signal, a direction signal and an output enable signal. As the selection signal is asserted the invention functions as a line driver, and as the selection signal is negated the invention functions as a bidirectional transceiver.

Abstract: An apparatus for showing a digitized NTSC-encoded video signal on an NTSC or PAL color television screen includes a system memory unit for storing the digitized video signal therein. A sync generator provides NTSC or PAL horizontal and vertical sync signals depending upon the type of color television screen in use. A sync delay and shading circuit provides an appropriate delay to the PAL horizontal and vertical sync signals when a PAL color television screen is in use. The horizontal and vertical sync signals control the cathode ray tube (CRT) unit to access the digitized video image in the system memory unit. The sync delay and shading circuit also disables the CRT control unit, a color burst generator, a (B-Y) and an (R-Y) color difference digital-to-analog (D/A) converter and a luminance and sync D/A converter during a 100 scan line period in which no video image is being displayed when the PAL color television screen is in use.