Abstract: The present invention provides a digital bus circuit comprising: a bus conductor having two sections each connected to a pass circuit, each bus section being connected to two bus interfaces for respective circuits; at least three of the bus interfaces comprising a tri-state output buffer having a tri-state mode and one or more logic output modes; wherein in a unitary bus mode the tri-state output buffers are arranged such that only one of said output buffers is not in a tri-state mode, and the pass circuit is arranged to substantially couple said bus sections; and wherein in a dual bus mode the tri-state output buffers are arranged such that only one of the output buffers connected to each bus section is not in a tri-state mode, and wherein the pass circuit is arranged to substantially isolate said bus sections.

Abstract: A feedback controller in a PWM amplifier comprises a signal input for receiving a pulse width modulated (PWM) input signal (Vin) whose duty cycle represents a desired analogue output signal. A feedback loop filter 518 generates a filtered error signal (Vint) comprising a filtered representation of differences between the input signal (Vin) and a feedback signal (Vfb). A comparator (520) compares the filtered error signal with a reference to generate a provisional PWM switching control signal (C) for controlling the PWM amplifier (500). A pulse conditioner (532) receives both the provisional PWM switching control signal (C) and the PWM input signal (X=Vin) and outputs to the amplifier (500) a conditioned PWM switching control signal (Y), modified in accordance with predetermined constraints in relation to the PWM input signal.

Abstract: An analog circuit for processing analog signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices. The circuit includes a first transistor device having a thin oxide thickness, and a second transistor device having a thicker oxide thickness. A voltage pulse protection is arranged to maintain the operating voltage of the thin oxide transistor in the presence of a rapidly rising voltage waveform (e.g. ESD), or at least to mitigate its effect on the thin oxide transistor device. Preferably a cascode based op amp structure is implemented.

Abstract: A current sensing circuit for sensing the current through a main switch, such as the PMOS or NMOS switches of a switching regulator, is disclosed. The circuit includes a mirror switch, said mirror switch being substantially similar to said main switch but with a smaller aspect ratio, a difference amplifier for ensuring that the voltage across said first leg and across said second leg are substantially equal and thereby to derive from said mirror switch a sensing current nominally equal to a current flowing in said main switch divided by a sensing ratio, a current source for producing a quiescent current in said difference amplifier and a compensatory device for compensating for said quiescent current such that said current sensing circuit can sense currents in the main switch which are smaller than the quiescent current multiplied by the sensing ratio. The compensatory device may be one or two switches essentially similar to the mirror switch.

Abstract: A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within the delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages.

Abstract: The present invention relates to Class-D amplifiers, and in particular to bit-flipping sigma-delta modulator (SDM) implementations of such amplifiers. Such amplifiers are particularly although not exclusively suitable for audio equipment such as hi-fi and personal music amplifiers. The present invention provides a bit flipping sigma delta modulator (BF SDM) having a multiple feedback loop filter structure. The modulator comprises a quantiser coupled to a bit flipping means, a look ahead quantiser to determine the next quantiser output, and a controller which determines whether to change the output of the bit flipping circuit. The modulator comprises a feedback loop arranged to add feedback from the output of the modulator to its input. The modulator comprises compensation circuit to adjust the states of the modulator in order to correct for bit flipping of the output of the quantiser. This adjusts the input to the quantiser to correspond to an input having feedback from a non bit flipped quantiser output.

Abstract: The present invention relates to pulse width modulation (PWM) modulators, especially but not exclusively for digital audio applications; and to quantizers and power switching for the same. The present invention provides a pulse width modulation (PWM) modulator or converter having a guard band quantizer arranged to block low level signal inputs to the modulator in order to prevent narrow width output pulses. This arrangement is particularly advantageous when applied to tri-level PWM modulators, but can also be applied to other level PWM modulators such as bi-level for example. Quantization noise can be reduced by implementing the quantizer in a noise shaper circuit (or possibly a SDM) having loop feedback.

Abstract: The present invention relates amplifiers using metal oxide semiconductor based integrated circuits. The present invention is particularly but not exclusively related to audio application mixed signal chips. The present invention provides an analog circuit for processing analog signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness. Preferably a cascode based op amp structure is implemented.

Abstract: An analogue to digital converter (ADC) of the recirculating type is described. In one embodiment, the ADC is composed of three storage and residual determination units, which, in cooperation with an operational amplifier, and suitable comparator means, are operable to re-present residual signals for analogue to digital conversion. To enhance settling at the beginning of a cycle, the first storage and residual determination unit is used once, with remaining recirculation being conducted between the other two storage and residual determination units. Another embodiment presents a recirculating ADC stage which comprises a plurality of capacitor banks operable to be switched into and out of connection with other components of the ADC stage, in order to recirculate residual values for calculation of further bits of a digital output. Each bank comprises a plurality of capacitors, and cooperating switching means for connecting each bank in turn with the other components.

Abstract: The present invention relates to digital to analog converters, and especially but not exclusively to switched capacitor digital to analog converters (DACs) for digital audio signals. The present invention provides a switched capacitor DAC for converting a digital signal and comprising a feedback capacitor coupled between an input and an output of an operational amplifier; a charging capacitor and a switching arrangement arranged during a charging period to couple a first side of said charging capacitor to a first reference voltage or a second reference voltage dependent on said digital signal, the switching arrangement further arranged during said charging period to couple a second side of the charging capacitor to the second reference voltage or the first reference voltage in anti-phase to the reference voltage coupled to said first side of the charging capacitor; the switching arrangement further arranged during a settling period to couple said charging capacitor to said feedback capacitor.

Abstract: The present invention relates to noise shaping, especially although not exclusively for digital audio signal processing; and in particular for PCM-PWM converters in a digital amplifier.

Abstract: An amplifier is disclosed, having an input stage connected to an output stage. The input stage is connected between a positive supply rail and a ground rail and has an input terminal arranged to receive an input signal. The output stage is connected between a positive supply rail and a negative supply rail and has an output terminal. The output stage is adapted to generate an output signal, which is dependent on a received input signal, at the output, and is further adapted such that, in use, a quiescent voltage at the output terminal is at a selected value between a voltage on the positive supply rail and a voltage on the negative supply rail. For driving a grounded load, the quiescent output voltage is preferably zero volts. In preferred embodiments, the input and output stages are formed on a common substrate using CMOS technology, the output stage including one or more NMOS devices having a triple-well structure. A corresponding method of driving a grounded load is also disclosed.

Abstract: This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters. A differential switched capacitor digital-to-analogue (DAC) circuit (500) comprises first and second differential signal circuit portions (500a,b) for providing respective positive and negative signal outputs with respect to a reference level, and has first and second reference voltage inputs (112,114) for receiving respective positive and negative references. Each of said first and second circuit portions comprises an amplifier (102a,b) with a feedback capacitor (104a,b), a second capacitor (106a,b), and a switch (108a,b, 110a,b) to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor.

Abstract: The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.