Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Abstract: Class D amplifier circuits for amplifying an input signal. The amplifier has an H-bridge output stage and thus has switches for switchably connecting a first output to a first voltage, e.g. Vdd, or a second voltage (e.g. ground) and for switchably connecting a second output to the first or second voltages. A switch controller is configured to control the H-bridge stage so as to vary between a plurality of states including at least a first state in which the outputs are both connected to the first voltage and a second state in which the outputs are both connected to said second voltage. The switch controller is configured to vary the proportion of time spent in the first state relative to the second state based on an indication of the amplitude of the input signal.

Abstract: The present invention provides an audio codec for converting digital audio signals to analogue audio signals, the audio codec comprising: two digital audio bus interfaces for coupling to respective digital audio buses; a digital-only signal path between the two digital audio bus interfaces, such that no analogue processing of the audio signals occurs in the digital-only signal path.

Abstract: A DC-to-DC converter generates multiple outputs from a single input supply using a single inductor. The inductor current can be changed rapidly by connecting the input voltage in either direction across the inductor using switches A to F. In use, current flows from the input supply through the inductor to an output during a charge phase, then current flows from ground through the inductor to the output in a discharge phase. The level of inductor current at the end of the discharge phase is stored. Before the next charge phase for the same output, the input supply is connected across the inductor in a slew phase to bring the inductor current to the stored level. This reduces crosstalk between outputs having different power requirements. Variable frequency noise in the converter is reduced by giving each output the same total time (slew phase+charge phase+discharge phase).

Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

Abstract: A pattern detection circuit detects a pattern in a received bit stream, for example a repetitive 8-bit silence pattern in a stream of digital audio data. Summing circuitry forms during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in the bit stream; and forms during second alternate time periods an inverse of a sum of a second sequence comprising the predetermined number of alternate bits in the bit stream. It is then determined whether successive sums formed by the summing circuitry are equal.

Abstract: A circuit for preventing clipping in an Automatic Level Control (ALC) or Limiter, where the amplitude of the signal above the clipping point is estimated, then the signal level is automatically reduced over a defined period substantially equal to the feedforward delay in the ALC/Limiter. By adaptively controlling, based on the excess amplitude and the delay time available, an attack rate used in the ALC/Limiter to reduce the gain applied to an input signal, it can be ensured that the output amplitude is brought within the clipping level sufficiently quickly to prevent audible clipping.

Abstract: A look-up table (LUT) is arranged as a plurality of rows each indexed by an index value and storing at least a coefficient for each index value for use in processing digital data. The LUT contains repeated sections in which m coefficients stored for successive index values form a cycle. The number m is not an integer power of 2. For example the LUT may be used when converting a digital count to a gain in dB, in which case m may be 6 or 12, the coefficients representing dB or fractional-dB steps in gain. The LUT contains n additional blank rows inserted after every repeated section of m rows storing the cycle of m coefficients, n being 1 or more and (m+n) being an integer power of two (such as 8 or 16). By feeding an initial index value through encoding logic which takes account of the additional rows, it can be ensured that these are never indexed. Thus, a sparse-coded LUT is provided.

Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

Abstract: A method of generating a voltage supply (Vout+, Vout?) from a single input supply (+VDD), comprising connecting at least one flying capacitor (Cf) to at least one reservoir capacitor (CR1, CR2) and to the input supply in repeated cycles so as to generate a voltage on said reservoir capacitor, the cycles differing between at least two modes so that each mode generates a different voltage on said reservoir capacitor the method including changing from an existing one of said modes to enter a new one of said modes during operation, and operating in at least one transitional mode for a period prior to entering fully said new mode.

Abstract: An amplifier power-down apparatus for suppressing transient signals in a circuit, for example an audio circuit, comprising a reference voltage generator circuit for generating a reference voltage. The reference voltage generator circuit comprises a capacitor for maintaining the reference voltage at a desired level. The amplifier power-down apparatus comprises a discharge control circuit for controlling the operation of the reference voltage generator circuit during power-down. The discharge control circuit comprises an amplifier with a positive feedback path for controlling a current flow from the capacitor during power-down.

Abstract: An amplifier start-up apparatus for reducing transient signals in a circuit, for example an audio circuit, comprising a reference voltage generator circuit for generating a reference voltage. The reference voltage generator circuit comprises a capacitor for maintaining the reference voltage at a desired level. The amplifier start-up apparatus comprises a control circuit for controlling the operation of the reference voltage generator circuit during power-up. The control circuit comprises an amplifier with a positive feedback path for controlling a current flow to the capacitor.

Abstract: There is provided an amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.

Abstract: A MEMS transducer includes a substrate, a membrane layer and a back-plate layer. The membrane layer is supported by the substrate. The back-plate layer is supported by the membrane layer and includes a respective sidewall portion and a respective raised portion. One or more columns, separate from the sidewall portion of the back-plate layer, connect the back-plate layer, the membrane layer and the substrate.

Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

Abstract: The invention provides a digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible, through the use of a low latency signal processing chain consisting of analogue-to-digital conversion, digital processing and digital-to-analogue conversion. The arrangement converts the analogue signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context.

Abstract: Electrical power from an input voltage supply is converted to first and second output voltages of opposite polarities using a single inductor (L) and only four principal switches (S1, S2, S4, S6). In contrast to known circuits, none of the switches is exposed to voltages greater than the input voltage (V1). In a first type of charging cycle (FIG. 5(a)-(c)), the first output voltage (V2+) is obtained from the input voltage supply through the inductor. In a second type of charging cycle (FIG. 5 (d)-(f)), the second output voltage (V2?) is obtained from the first output voltage via the intermediate step of storing energy in the same inductor as is used in the first type of charging cycle. Auxiliary switches (S7a, S7b) can be operated in wait states between cycles of the first and second type.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.

Abstract: An apparatus is provided for monitoring and controlling a device under test, the device under test comprising a plurality of registers, each register having a register value and comprising a plurality of data bits for controlling a setting or settings of the device under test. The apparatus comprises display means for displaying an interactive register map to a user. The interactive register map is configured to display a plurality of register values simultaneously, and further adapted to display one or more data fields corresponding to each register value, each data field relating to one or more of the data bits and having a first indicator for representing a corresponding device setting. In this manner, a user can readily appreciate which device settings are controlled by the same register value, and hence can be written simultaneously.

Abstract: A pattern detection circuit detects a pattern in a received bit stream, for example a repetitive 8-bit silence pattern in a stream of digital audio data. Summing circuitry forms during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in the bit stream; and forms during second alternate time periods an inverse of a sum of a second sequence comprising the predetermined number of alternate bits in the bit stream. It is then determined whether successive sums formed by the summing circuitry are equal.