Abstract: A capacitive transducer circuit includes a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analog signal on an input terminal, the first analog signal being generated by the capacitive transducer, and to generate a second analog signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. A switched capacitor filter circuit may be arranged between the voltage source and the transducer and may be arranged to filter the output of the voltage source.

Abstract: A signal processing circuit is intended for use in a noise reduction system, which produces a target filter characteristic that would achieve optimal noise cancellation, the target filter characteristic including a resonant peak at a first frequency. The signal processing circuit comprises an analogue filter, which has an amplitude response that has a peak or trough at a center frequency, and has a phase response that switches polarity at the center frequency and tends to zero with increase or reduction in frequency away from the center frequency. The center frequency in the amplitude response is substantially equal to the first frequency. The analogue filter may be in the form of a series inductive-capacitive-resistive circuit, where the inductive component is in the form of a gyrator.

Abstract: Electrical power from an input voltage supply is converted to first and second output voltages of opposite polarities using a single inductor (L) and only four principal switches (S1, S2, S4, S6). In contrast to known circuits, none of the switches is exposed to voltages greater than the input voltage (V1). In a first type of charging cycle (FIG. 5(a)-(c)), the first output voltage (V2+) is obtained from the input voltage supply through the inductor. In a second type of charging cycle (FIG. 5 (d)-(f)), the second output voltage (V2?) is obtained from the first output voltage via the intermediate step of storing energy in the same inductor as is used in the first type of charging cycle. Auxiliary switches (S7a, S7b) can be operated in wait states between cycles of the first and second type.

Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.

Abstract: A charge pump circuit, and associated method and apparatuses, for providing a split-rail voltage supply, the circuit having a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of said states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

Abstract: A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency.

Abstract: A clock synchronizer for generating a local clock signal synchronized to a received clock signal. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider.

Abstract: The present invention provides a method of operating a digital audio device, the method comprising: receiving a voice call; receiving another digital audio signal which is not a voice call; mixing the two received signals; transmitting the mixed signal wirelessly to another device.

Abstract: A light source is protected by selectively coupling a shunt path in parallel with the light source, such that current is diverted away from the light source and through the shunt path. A detection circuit detects the current flowing in the shunt path when the shunt path is connected in parallel with the light source. A comparator determines whether the current flowing in the shunt path exceeds a predetermined threshold and, if so, prevents or limits the flow of current when the shunt path is disconnected from being in parallel with the light source. In this way, a current detector is provided for monitoring the flow of current in a shunt path, the current detector being configured to disable or limit the flow of current through a light source when a predetermined threshold is reached.

Abstract: A driver apparatus is provided for controlling a light source array comprising at least first and second light sources, the light source array used for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. The driver apparatus comprises a single integrated circuit comprising processing means for processing image data received from the detector, a switching array comprising at least first and second switches for switching the respective first and second light sources, and a current source for controlling the flow of current through the light sources. In this way the LED switching circuitry that controls an LED array is 15 placed on the same integrated circuit (i.e. monolithic circuit) as the analogue processing circuitry that processes the image data, with the current source controlling the flow of current through the LEDs in the LED array.

Abstract: A MEMS device comprising a flexible membrane that is free to move in response to pressure differences generated by sound waves. A first electrode mechanically coupled to the flexible membrane, and together form a first capacitive plate. A second electrode mechanically coupled to a generally rigid structural layer or back-plate, which together form a second capacitive plate. A back-volume is provided below the membrane. A first cavity located directly below the membrane. Interposed between the first and second electrodes is a second cavity. A plurality of bleed holes connected the first cavity and the second cavity. Acoustic holes are arranged in the back-plate so as to allow free movement of air molecules, such that the sound waves can enter the second cavity. The first and second cavities in association with the back-volume allow the membrane to move in response to the sound waves entering via the acoustic holes in the back-plate.

Abstract: There is provided a method of controlling a noise cancellation system, the noise cancellation system being for use in a device comprising a speaker for receiving a wanted signal and generating a sound signal therefrom, and the noise cancellation system comprising: a digital filter, for generating a noise cancellation signal from an input signal representative of ambient noise; and an output for applying the noise cancellation signal to the speaker in addition to the wanted signal to generate a sound signal from which the ambient noise has been at least partially cancelled. The method comprises: determining a resonant frequency of the speaker; based on the determined resonant frequency, selecting a set of filter coefficients; and applying the selected set of filter coefficients to the digital filter.

Abstract: A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the component drives the bus line to its opposite state, and, when the signal takes a second binary value, binary “0”, the component does not actively drive the bus line. During arbitration, each arbitrating component writes a unique arbitrand onto the bus, and arbitration is lost by each component that writes a binary “0” when at least one other component writes a binary “1”. The components preferably do not use transition-dominant signalling when transmitting data payloads. For such traffic they actively drive the binary “0”s as well as binary “1”s.

Abstract: In a switched-capacitor circuit such as a DAC, charges are accumulated by a plurality of sampling capacitors in dependence upon input digital data during a sampling phase; then, during a sharing phase these charges are shared with a holding capacitor which is connected across an opamp. In the so-called bipolar charging type switched-capacitor DAC, the signal provided by the sampling capacitors is doubled by connecting their opposite sides to positive and negative reference voltages during the sampling phase. However, parasitic capacitances associated with the sampling capacitors then cause a disturbance to the input of the operational amplifier during the sharing phase. By equalising the input sides of the sampling capacitors to a reference voltage, prior to the sharing phase, this disturbance is avoided thereby allowing a low-power opamp to be employed in the DAC. This equalising can be achieved by adding a short equalising clock phase between the usual sampling and sharing clock phases of the DAC.

Abstract: A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout?). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor.

Abstract: A MEMS device comprising a flexible membrane that is free to move in response to pressure differences generated by sound waves. A first electrode mechanically coupled to the flexible membrane, and together form a first capacitive plate. A second electrode mechanically coupled to a generally rigid structural layer or back-plate, which together form a second capacitive plate. A back-volume is provided below the membrane. A first cavity located directly below the membrane. Interposed between the first and second electrodes is a second cavity. A plurality of bleed holes connect the first cavity and the second cavity. Acoustic holes are arranged in the back-plate so as to allow free movement of air molecules, such that the sound waves can enter the second cavity. The first and second cavities in association with the back-volume allow the membrane to move in response to the sound waves entering via the acoustic holes in the back-plate.

Abstract: A converter including an inductor (L), a first switch (SW1, S1) connected between an input terminal (Vin) and the inductor, a diode/switch (D1, S2), connected between the first end of the inductor and ground, a diode/switch (D2, S3) connected between the inductor and an output terminal (Vout), and a second switch (SW2, S4) coupled between inductor and ground. A current sensor senses current in the first switch (SW1, S1) as a measure of inductor current. Waveform generators (31, 32) generate buck and boost slope compensation ramps (RMP-BUCK, RMP-BOOST). Control logic (10) opens and closes the switches every clock period at individual duty cycles determined using a feedback signal derived from the output terminal, the sensed current and the slope compensation ramps. The slope compensation ramps are mutually offset such that current sensing is needed only while the first switch (SW1, S1) is closed.

Abstract: A feedforward ambient noise reduction arrangement (10) includes, within a housing, a loudspeaker device for directing sound energy into an ear of a listener. Disposed externally of the housing, and positioned to sense ambient noise on its way to the listener's ear, are plural microphone devices (21-15) capable of converting the sensed ambient noise into electrical signals for application to the loudspeaker to generate an acoustic signal opposing the ambient noise. Importantly, the overall arrangement is such that the acoustic signal is generated by said loudspeaker means in substantial time alignment with the arrival of said ambient noise at the listener's ear.

Abstract: The present invention provides an audio codec for converting digital audio signals to analogue audio signals, the audio codec comprising: two digital audio bus interfaces for coupling to respective digital audio buses; a digital-only signal path between the two digital audio bus interfaces, such that no analogue processing of the audio signals occurs in the digital-only signal path.

Abstract: On a communications bus, a relatively low frequency timing reference is distributed by regularly transmitting numbers that represent its instantaneous phase. An active framer component maintains a wrapping count of root superframes and, during each block, transmits in encoded form an expected value for the root superframe count at the start of the following block.