Abstract: An auto slurry deliver fine-tune system and a method using the system is discloses. A slurry flow system varies the flow rate of the slurry in a CMP system and the distance between the slurry injector and the polish head of the CMP system. A current detect system detects the current driving the turn-table of the CMP system. Moreover, a judgement system determines whether the current is minimum in order to determine that the flow rate and the distance are optima.

Abstract: A self-aligned fabricating process and a structure of ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then forming a plurality of parallel stacked gates above the substrate. The device isolation lines and the stacked gates are perpendicular to each other. A plurality of first insulation layers is formed such that an insulation layer is formed over each stacked gate. Spacers are also formed over the sidewalls of each stacked gate. A plurality of source arrays and drain arrays are formed in the substrate between neighboring stacked gates. The source and drain arrays are parallel to the stacked gates, with a source array and a drain array formed in alternating positions between the stacked gates. Each source array comprises a plurality of source-doped regions located between the device isolation lines respectively. Similarly, each drain array has a plurality of drain-doped regions located between the device isolation lines.

Abstract: This invention discloses a method for forming an attenuated phase-shifting mask, including following steps. A transparent plate is provided, on which a phase-shifting layer, opaque layer, and undeveloped photoresist layer being stacked on the transparent plate successively. A first part of the photoresist layer is removed until exposing a first region of the opaque layer. The first region of the opaque layer is removed for exposing parts of the phase-shifting layer. A second part of the photoresist layer is removed for exposing a second region of the opaque layer. The exposed phase-shifting layer is then etched by employing the opaque layer as an etching mask. Then the exposed opaque layer and photoresist layer are successively remove, thus forming a complete attenuated phase-shifting mask.

Abstract: A method of forming an anti-reflective coating is described. A film is formed on a substrate. A first layer of an anti-reflective coating layer Is deposited on the film by chemical vapor deposition using a canrier gas, an organic halide gas and a hydrogen halide gas as gas sources. A second layer of the anti-reflective coating layer is formed on the first layer of the anti-reflective coating layer by chemical vapor deposition using a carrier gas and an organic halide gas as gas sources. A photoresist layer is formed on the second layer of the anti-reflective coating layer.

Abstract: An auto slurry deliver fine-tune system and a method using the system is discloses. A slurry flow system varies the flow rate of the slurry in a CMP system and the distance between the slurry injector and the polish head of the CMP system. A current detect system detects the current driving the turn-table of the CMP system. Moreover, a judgement system determines whether the current is minimum in order to determine that the flow rate and the distance are optima.

Abstract: A process for fabricating a capacitor suitable for forming a bottom electrode layer of the capacitor on a substrate. First, a first dielectric layer is formed on a substrate. Then, a portion of the first dielectric layer is removed to form a contact hole. A conductive plug is formed within the contact hole. A seed layer is formed on the conductive plug. A sacrifice layer is formed on both the seed layer and the first dielectric layer. A predetermined region of the sacrifice layer is removed to form a recess so as to expose the seed layer. Then, a bottom electrode layer is formed by electroplating within the recess. The sacrifice layer is removed afterwards. Finally, a second dielectric layer and a top electrode layer are formed on the bottom electrode layer in sequence. The present invention is characterized in that it does not require a direct etching process on a platinum material to. form the bottom electrode layer.

Abstract: A method of forming dual damascene structure is disclosed. A pad oxide layer, a barrier layer and an organic dielectric layer are formed in sequence on a substrate with the conducting line and the organic dielectric layer is etched with a patterned photoresist as a mask to form trenches therein. Next, an anisotropic thickness oxide layer is formed on the substrate by the plasma enhanced chemical vapor deposition (PECVD). Then, the anisotropic thickness oxide layer, the barrier layer and the pad oxide layer are etched with a patterned photoresist as a mask to form vias therein until the conducting line is exposed. Finally, a metal layer is deposited on the substrate and fills the vias and the trenches to form the dual damascene structure.

Abstract: An auto slurry deliver fine-tune system and a method using the system is discloses. A slurry flow system varies the flow rate of the slurry in a CMP system and the distance between the slurry injector and the polish head of the CMP system. A current detect system detects the current driving the turn-table of the CMP system. Moreover, a judgement system determines whether the current is minimum in order to determine that the flow rate and the distance are optima.

Abstract: An apparatus and method for conditioning the polishing pad of CMP system by employing a multi-zone conditioner, or dresser. The conditioner comprises a plurality of rollers or disks, which can be well tuned to make down-pressure and rolling speed of the rollers or disks to the extent as desirable. The conditioner further comprises driving means for rotating the polishing rollers or disks. It can make a better uniformity of the pad conditioning and improve the profile of the polished wafers. The apparatus and method for conditioning the polishing pad can be especially used to compensate the uniformity of the incoming films, or the pre-CMP films.

Abstract: A method for forming salicide on the peripheral logic region of the embedded DRAM without using a salicide block mask layer to protect the memory cell region of the embedded DRAM and without oxide wet dip to prevent oxide loss in the field oxide is disclosed. Additionally, the landing plug process in the memory cell region is performed by a self-aligned contact (SAC) etching process with a silicon nitride layer as an etching protective layer.

Abstract: A structure of dynamic random access memory with slanted active regions, comprising: a substrate; a plurality of slanted active regions formed on the substrate, wherein each of the plurality of slanted active regions has a bit line contact; a plurality of word line regions formed on the substrate to control transistors of the dynamic random access memory; a plurality of bit line regions formed on the substrate, wherein each of the bit line regions cross the bit line contact hole so that the bit line contact hole is completely covered by the bit line regions; a plurality of capacitors formed between the plurality of bit line regions.

Abstract: A method for forming organic anti-reflective coating (ARC) is disclosed in the present invention. A substrate is provided and an ARC is deposited on the substrate using reactive gas. The reactive gas comprising compound gas containing carbon atom, hydrogen atom and halogen atom, where said compound gas has a general formula of CxHyXz, X is halogen element, x ranges from 0 to 5, y ranges from 0 to 9 and z ranges from 0 to 9. The reactive gas could be injected into a chamber with carrier gas, which is helium gas or argon gas.

Abstract: A method of forming ESD protective transistor is disclosed, which is performed by ion implant into the drain contact hole of the ESD protective transistor, wherein the contact hole are fabricated simultaneously with the gate contact holes of the functional transistor and of the ESD protective transistor. Both of the transistors have a respective metal silicide layer cap the polysilicon layer to prevent depleted region formed in the poly-gate for ion implant using p type ions. The p type ions are to increase the instant current tolerance. Alternatively, the ion implant is using n type ions to increase the punchthrough ability of the ESD protective transistor. In the latter case, the metal silicide layer in the gate regions of both transistors is optional.

Abstract: A method for embedded flash cell fabrication beyond 0.35 &Xgr;m generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxide window and capacitor coupling area. Next, a conventional photolithogrpahy and etching method is used to formed a patterned photoresist on the substrate and expose flash cell areas. Then N-type conductive dopants are implanted into the substrate. For 0.35 &mgr;m generation, the concentration of dopant is increased to 5El7˜1El9 atoms/cm3. Next, the patterned photoresist layer are removed and thicker tunnel oxide and thinner gate oxide layer are formed in one processing step. Next, a doped polysilicon layer is deposited by using a conventional chemical vapor deposition over the tunnel oxide layer to serve as the floating gate of the flash cell.

Abstract: A method for planarizing a semiconductor wafer. An insulation layer is formed over the wafer. A spin-on-glass layer is coated over the insulation layer. Subsequently, the spin-on-glass layer is baked to smooth out its upper surface. A chemical-mechanical polishing process is carried out to planarize the insulation layer. The method eliminates recess cavities in the more loosely packed device region of the insulation layer after a planarization process.

Abstract: A method for forming a DRAM cell with a crown full metal capacitor electrode with integrated selective tungsten contact hole. When the MOSFET devices are defined, a metal landing pad with Ti/TiN/W/TiN is first deposited and etched. After an insulating layer is deposited and node contact is formed, a CVD TiN layer is deposited and etched to form TiN spacers on the node contact sidewalls. Next, selective tungsten is formed in the node contact and use reactive ion etching to etch back. Thereafter, another insulating layer is deposited and the crown pattern opening is formed. Then, a TiN/W metal layer is deposited to serve as the bottom electrode of the stacked capacitor. After a photoresist layer is formed, then a chemical mechanical polishing method is used to remove portions of the photoresist layer and the TiN/W metal layer by using insulating layer as an polishing stop. The remaining photoresist and insulating layer are removed.

Abstract: A method of forming a DRAM capacitor comprises the following steps in the sequence set forth. First, a first silicon oxide layer is formed on a substrate, and a nitride layer is then deposited on the first silicon oxide layer. Next, uses photolithograpy and etching process to define a contact hole, and then, fills polysilicon into the contact hole. Further, the partial polysilicon in the top contact hole is removed, sequently, W-metal (selective tungsten metal) is filled into the blank part in the top contact hole. Then, a second silicon oxide layer is deposited on surfaces of the nitride layer and the W-metal (selective tungsten metal). Subsequently, etchs back the second silicon oxide layer to form a trench, thus, the W-metal (selective tungsten metal) would be exposed in the trench.

Abstract: The method for forming a flash memory cell mainly includes the steps as follows. At first, a semiconductor substrate having isolation regions thereon and having a well region provided between the isolation regions is provided. A tunnel oxide layer is formed on the well region and a first silicon layer is formed over the substrate. A dielectric layer is formed on the first silicon layer and a portion of the first silicon layer and the dielectric layer is removed to define a control gate opening within the first silicon layer on a portion of the well region. Next, the substrate is doped in the region under the control gate opening to adjust a threshold voltage of the flash memory cell. A gate oxide layer is grown from the substrate in the control gate opening and a second silicon layer is formed on the substrate to fill within the control gate opening and to cover the remaining dielectric layer.

Abstract: The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region.

Abstract: A method for manufacturing an erasable programmable memory is disclosed, and an enlargement of the coupling area between control and floating gates is employed to increase the capacitive-coupling ratio. Firstly, the isolation regions are formed on the substrate. A polysilicon layer is formed on a portion of the control region of the substrate to form an uneven silicon surface. An ion implantation is carried out to form the doped tunnel region and the control gate. A tunnel oxide layer and a non-tunnel oxide layer are formed on the doped tunnel region, and an inter-poly dielectric is formed on the control gate. A floating gate is now deposited on the doped tunnel region and the control gate. Then an inter-layer dielectric is formed and etched to provide the isolation and connect between control gate and interconnects.