Abstract: A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A conducting plug is then formed into the contact hole. Next, a dielectric layer is formed on the semiconductor substrate and the conducting plug. The dielectric layer is etched by photolithography to form an opening for exposing the top surfaces of the conducting plug and a portion of the semiconductor substrate. A plurality of discrete rugged polysilicon grains are formed on the surfaces of the dielectric layer, the conducting plug and the semiconductor substrate. The dielectric layer is next etched to form a plurality of cavities on a top surface of the dielectric layer by using the plurality of discrete rugged polysilicon grains as an etching mask.

Abstract: The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the first via hole. Then, an etching is used to etch the layer. A residual portion of the layer is located at the lower portion of the first via hole. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Then, the oxide and the first dielectric layer are etched to define a second via hole. A further polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the gate.

Abstract: The method for forming inter-metal dielectric layers in a metallization process mainly includes the following steps. At first, a semiconductor substrate having interconnection structures formed thereon is provided. A liner layer is formed to cover the interconnection structures and the substrate, and a first dielectric layer is formed on the liner layer. A planarization stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the planarization stop layer, wherein the second dielectric layer has a higher removal rate than the planarization stop layer in a planarization process. Finally, the substrate is planarized by removing portions of the second dielectric layer until portions of the planarization stop layer is presented.

Abstract: A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A polysilicon contact is then formed to fill into the contact hole. A metal layer is formed on the substrate and the polysilicon contact. Next, a silicon catching layer is formed on the metal layer. An annealing step is performed to substitute the silicon contact with a portion of said metal layer for forming a metal contact, wherein the silicon atom are driven to react with the silicon catching layer for forming a compound layer underneath the silicon catching layer. After the metal layer, the silicon catching layer and the compound layer are removed, the first conduction layer is formed on the substrate and the metal contact to serve as a bottom electrode. Then, a dielectric layer is formed along the surface of the first conduction layer. The second conduction layer is next formed on the dielectric layer to serve as a top electrode.

Abstract: The present invention discloses a structure of metal interconnection lines in integrated circuits for improving thermal conductivity therein. In the structure, a silicon nitride layer is formed underneath a first metal pattern of integrated circuits. Moreover, a silicon nitride plug is formed between two adjacent metal patterns and it serves as a thermal conductor. At least one metal plug in dielectric layers between the metal patterns is an electrical connection of integrated circuits. The present invention also discloses a method for fabricating the structure as mentioned above.

Abstract: The present invention proposed a method for fabricating electrodes, especially the electrodes for capacitors which incorporates the application of high dielectric constant dielectrics. The present process avoids the conventional etching issues with conductive materials, especially conductive materials like platinum (Pt), Ruthenium oxide (RuO2), Iridium oxide (IrO2) and etc. A method in the invention for fabricating electrodes on a semiconductor substrate includes the following steps. After a first step forming a node-defining layer on the substrate, a subsequent step of patterning the node-defining layer is carried out to form a plurality of node openings within the node-defining layer. A first conductive layer is formed to fill into the openings and to form over the node-defining layer. A step of removing a portion of the first conductive layer is performed to the portion which is located outside the openings.

Abstract: A semiconductor fabrication method is provided for fabricating a capacitor with a low-resistance electrode structure in a mixed-mode integrated circuit (IC) device. The first step is to prepare a semiconductor substrate having a first area where a gate and a pair of source/drain regions are defined and a second area where a first electrode is defined. A first dielectric layer is then formed to cover the first electrode. After this, a doped polysilicon layer, a metal silicide layer, and a second dielectric layer are successively formed over the first dielectric layer, which in combination constitute a second electrode for the capacitor. The incorporation of the metal silicide layer in the second electrode can significantly help reduce the overall resistance of the second electrode, thereby allowing a considerable increase to the overall performance of the resulting IC device. Moreover, the method is less complex in process and thus easier to perform than the prior art.

Abstract: A method for fabricating DRAM capacitor dielectric layer with high permittivity is disclosed. In the first preferred embodiment, the process temperature is about 700° C. or below. Thus this embodiment is apt to utilize for DRAM with metal silicide transistor. In the processes, the multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer. The second preferred embodiment, the processes uses different CVD method to deposit multiple thin silicon nitride layers and thus pinhole defects are unmatched. Both of two embodiments provide capacitor dielectric layer with least leakage current so as to increase the capacitance.

Abstract: The present discloses a method of forming shallow trench isolation to prevent the dishing effect, the corner effect and provide an effective endpoint detection. The method includes these steps below. A pad oxide layer is formed on a semiconductor substrate. A first silicon nitride layer is formed on the pad oxide layer. A trench is formed in the substrate. A liner layer is formed on sidewalls and a bottom of the trench. A second silicon nitride layer is formed on the first silicon nitride layer and the liner layer. A polysilicon layer is formed on the second silicon nitride layer. A first silicon dioxide layer is formed on said polysilicon layer, thereby filling the trench with the first silicon dioxide layer. The first silicon dioxide layer is polished by performing a chemical mechanical polishing with a poly slurry. The polysilicon layer is oxidized to form a second silicon dioxide layer. The first silicon nitride layer and the second silicon nitride layer are removed.

Abstract: A method of fabricating a twin-tub capacitor is described in which a dielectric layer is defined to form multiple column structures, followed by forming a conductive layer over the column structures. The conductive layer on the top surface of the column structures are removed by chemical mechanical polishing to isolate each capacitor. The column structures are further removed to form a twin-tub capacitor.

Abstract: A method of fabricating a mask read-only memory. Before carrying out a code implantation, a coding mask is used as an etching mask to remove a portion of the inter-metal dielectric layer and the inter-layer dielectric layer above the coding positions, thereby forming a contact window. The code implantation is subsequently carried out so these ions can easily reach the coding positions via the contact opening.

Abstract: A method for fabricating a metal interconnect structure. A first insulating layer and a second insulating layer with a low dielectric constant are formed on a substrate in sequence. An opening is formed in the second insulating layer. A compact and high density third insulating layer is formed on the second insulating layer and in the opening to protect the second insulating layer from being damaged in a subsequent process for removing a photo-resist layer. A contact window is then formed in the third insulating layer at a bottom of the opening and the first insulating layer, so that a dual damascene opening is formed. The dual damascene opening is filled with metal with low resistivity to form the metal interconnect.

Abstract: A multi-exposure process. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk by the precondition of the fixed pitch. Moreover, the line width can be shrunk to a level even smaller than the resolving power of the stepper or the scanner. Additionally, by using the invention, the exposure energy, the exposure time and the exposure DOF can be fixed while the exposure process is performed. Therefore, the process window is increased and the yield is enhanced. Furthermore, the processing sequence according to the invention is simpler than the conventional photolithography processing sequence, so that the throughput can be increased.

Abstract: A multiple crown capacitor and a method of fabricating such a capacitor is described. The method is applicable to a substrate in which an isolation layer is formed on the substrate, with a node contact plug formed in the isolation layer. A sacrificial layer is then formed on the substrate followed by a patterning of the sacrificial layer to form a succession of openings above the node contact plug and its surroundings, exposing the isolation layer and a portion of the node contact plug upper surface. Thereafter, a conformal conductive layer is formed on the sacrificial layer and in the openings. A portion of the conductive layer, which is higher than the sacrificial layer, is removed, followed by removing the sacrificial layer to form a bottom electrode. A conformal dielectric layer and an upper electrode are sequentially formed on the bottom electrode to complete the formation of the capacitor.

Abstract: A method for stacked capacitor. The method utilizes a silicon nitride layer as an etching stop layer for removing the insulation layer on each side of a crown-shaped capacitor structure. As soon as the insulation layer is removed the silicon nitride layer is removed as well. In addition, a high-temperature oxide layer is formed over the inter-layer dielectric. The high-temperature oxide layer can prevent the formation of hemispherical grains on its surface when selective hemispherical grains are formed on the surface of an amorphous silicon layer.

Abstract: A method for manufacturing stacked capacitor. The method utilizes a manufacture method of a trench line and a via applied in dual damascene process to form a trench line and a via in a dielectric layer. Then, multi-amorphous silicon layers with different doping concentration are conformally formed on an exposed surface of the trench line and the via to serve as a bottom electrode of a double-sided double-crown-shaped capacitor. Furthermore, a phosphine (PH3) treatment process is performed after hemispherical grains are formed on the bottom electrode of the double-sided double-crown-shaped capacitor to increase the doping concentration of the bottom electrode surface of the capacitor. Moreover, a poly slurry having a high polishing selectivity of amorphous silicon to silicon nitride is used in a chemical mechanical polishing process during the formation of the double-sided double-crown-shaped capacitor to promote good uniformity of the polished wafer and make the polish end point available.

Abstract: A method of fabricating a capacitor is described in which a substrate comprises a transistor and a planarized insulation layer. An opening is formed in the insulation layer, exposing one of the source/drain of the transistor. A sacrificial plug is formed in the first opening. The insulation layer surrounding the first opening is removed to form a second opening and a certain thickness of the insulation layer is retained at the bottom of the second opening. The sacrificial plug is removed and simultaneously forming a node plug and a first electrode respectively in the first opening and on the bottom and side wall of the second opening. A dielectric layer is further formed on the surface of the first electrode and a second electrode is formed on the dielectric layer.

Abstract: A read-only memory structure and method of manufacture comprising the steps of sequentially forming a tunneling oxide layer, a first polysilicon layer, a bottom oxide layer and a silicon nitride layer over a semiconductor substrate having field oxide layers already formed thereon. A mask is used to pattern the various layers above the semiconductor substrate forming a floating gate out of the first polysilicon layer. Thereafter, a doped region in formed in the semiconductor substrate, and then a chemical vapor deposition method is used to form a top oxide layer and a second silicon nitride layer over the first silicon nitride layer. Subsequently, the second silicon nitride layer is etched back to form spacers on the sidewalls of the floating gate. Next, thermal oxidation is carried out so that the doped region is oxidized into an etching barrier layer while a silicon oxy-nitride layer is formed over the surface of the spacers. Thereafter, an annealing operation is performed to densify the oxide layer.

Abstract: The method includes forming a metal layer over a substrate. Subsequently, a discrete dot masking is deposited on the surface of the metal layer. A discrete rugged polysilicon or hemispherical grained silicon (HSG-Si) can be chosen as the discrete dot masking. The source gas used to form the discrete rugged polysilicon includes Si2H6 at a temperature of about 400 to 450° C. An anisotropically etching step is performed to etch the metal layer by using the discrete dot masking as an etching mask, thereby forming a surface pattern formed thereon. Then, the discrete dot masking is removed. The metal layer is patterned to a conductive line pattern. An organic material layer with low dielectric constant is formed on the patterned metal layer. A silicon oxide layer is successively formed on the organic material layer, followed by polishing the silicon oxide layer using a chemical mechanical polishing (CMP).

Abstract: A method of fabricating a shallow trench isolation (STI). The method forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer in the vicinity of an interface between a STI and a substrate. Then, a planarization process is performed, and the spin-on glass layer is annealed into an oxide layer with good thermal stability.