Abstract: A method for fabricating a capacitor is described. A dielectric layer and a polysilicon layer thereon are provided. A patterned oxide layer and spacers on the sidewalls of the patterned oxide layer are formed. The polysilicon layer is etched using the oxide layer and spacer as an etching mask. The oxide layer and spacer are then removed. A dielectric layer and a conductive layer are sequentially formed on the polysilicon layer.

Abstract: A method of manufacturing mask read-only-memory. The method includes forming a plurality of first and second active regions in designated locations on a substrate. Each first and second active region has a channel region and a source/drain region on both side of the channel. Subsequently, shallow trench oxide are formed within the channel regions of the first active regions, and then source/drain terminals are formed in the respective source/drain regions of first and second active regions. Finally, a gate terminal is formed over the channel region.

Abstract: The method for forming a capacitor in the present invention includes the steps as follows. At first, a multi-layer structure is formed on a semiconductor substrate, and the multi-layer structure is provided to have etching selectivity in etching neighboring layers in the multi-layer structure. A top dielectric layer is then formed on the multi-layer structure. A first opening is defined in the top dielectric layer, and a second opening is defined in the multi-layer structure under the first opening. Next, a wet etch is performed through the second opening to form at least two lateral openings in the multi-layer structure. Following the wet etch, a first conductive layer is formed conformably on the top dielectric layer, on sidewalls of the first opening and the second opening, and filled within the at least two lateral openings. A filling layer is then formed on the substrate, and the filling layer and the first conductive layer on the top dielectric layer are removed.

Abstract: A method of forming trench type DRAM capacitor. An insulation layer is formed on a substrate with a trench exposing a conductive region of the substrate. A first conductive layer is formed and conformal to a surface profile of the substrate. A photoresist layer is formed over the first conductive layer to fill the trench. A three-stage of etching process is carried out. A first stage of etching step is carried out to remove a portion of the photoresist layer, thereby exposing the first conductive layer. A second stage step is carried out to remove the first conductive layer by performing an isotropic dry etching step. The first conductive layer is slightly over-etched so that a portion of the first conductive layer inside the trench is also removed. Therefore, the first conductive layer inside the trench will be at a distance lower than a top surface of the insulation layer.

Abstract: A method of fabricating a landing pad. A gate electrode is formed on a substrate. The gate electrode has a top surface covered by a cap layer and a sidewall covered by a spacer. A polysilicon layer is formed to cover the gate. Using an oxygen based etchant to performed an isotropic chemical dry etching on the polysilicon layer, the polysilicon layer is planarized until a part of the spacer is exposed. The polysilicon layer is patterned to form a landing pad in contact with the substrate.

Abstract: A structure and method of fabricating a stacked capacitor which forms a hemispherical grain (HSG) polysilicon on the surface of a crown shaped amorphous silicon layer. By selective tungsten deposition, the HSG polysilicon and the amorphous silicon layer are displaced with a rough tungsten layer. A material with a high dielectric constant and a metal layer are formed in sequence as a dielectric layer and an upper electrode of the capacitor, so as to form a crown metal-insulator-metal (MIM) capacitor.

Abstract: A method for forming shallow trench isolation (STI) structures on a semiconductor substrate is disclosed. First a semiconductor substrate with a first area and a second area adjacent to the first area is provided. A mask layer is formed on the substrate, and is etched to expose portions of the substrate. A first photoresist is formed to cover the second area for exposing the first area. A first implanting procedure is performed with a titled angle to form first doping areas on the substrate encroaching into portions of the substrate covered by the first photoresist. The first photoresist is removed. A second photoresist is formed on the substrate to cover the first area for exposing the second area. And a second implanting procedure is done with a titled angle to form second doping areas on the substrate encroaching into portions of the substrate covered by the second photoresist. The second photoresist is removed.

Abstract: The invention describes a method of fabricating an integrated circuit used to prevent undercutting of an oxide layer due to wet etching. A semiconductor substrate has a gate formed thereon. A conformal oxide layer is formed to cover the gate. Then, a nitrogen ion implantation process is performed to introduce nitrogen ions into the surface of the conformal oxide layer. A high temperature thermal oxidation is performed in order to form Si--N bonds, that is, the nitrogen ions bonding with the silicon atoms of the conformal oxide layer, or to form Si--ON bonds, that is, the nitrogen ions bonding with the oxygen atoms of the conformal oxide layer. A dielectric layer, which covers the conformal oxide layer, is formed. Thereafter, the dielectric layer is etched back to form spacers on the sidewalls of the gate. A wet etching process is performed to remove a part of the conformal oxide layer exposed by the spacers.

Abstract: A method for forming interconnection plugs comprising the steps of providing a substrate having a dielectric layer formed thereon, wherein an opening exposing a pad area for connection with other structures is also formed in the dielectric layer. Next, a glue layer is formed over the pad area and the dielectric sidewalls of the opening. Subsequently, plug material is deposited into the opening forming a plug layer. This is followed by etching back the plug layer to return the plug material inside the opening to a level below the height of the dielectric layer. Then, a selective etching method having a high selectivity ratio between the dielectric layer and the plug layer is used to etch the dielectric layer. Finally, the dielectric layer and the plug layer are etched to almost the same level of height.

Abstract: A method for forming the dual damascene structure over a semiconductor substrate is disclosed in the present invention. First, a first dielectric layer is formed on the semiconductor substrate. An etch stopping layer is formed on the first dielectric layer. And a second dielectric layer is formed on the etch stopping layer. The second dielectric layer is then etched till the etch stopping layer to form a first opening and a second opening on the second dielectric layer. It is noted that the size of the second opening is bigger than that of the first opening. A polymer layer is next formed on the second dielectric layer and the etch stopping layer to close the first opening and to fill into a portion of the second opening for defining a third opening in the second opening.

Abstract: In this method for manufacturing a split-gate flash memory cell, a floating gate and a control gate are formed over a substrate, and then first spacers are formed on the sidewalls of the gate structure. Next, a polysilicon layer is deposited over the gate structure and the substrate, and second spacers are formed on the sidewalls of the polysilicon layer. A self-aligned ion implantation process is performed, using the second spacers as a mask, implanting ions into the semiconductor substrate to form a drain region. This maintains the channel length. After removing the second spacers, another ion implantation process is performed to create a source region in the semiconductor substrate. During the second implantation, the polysilicon layer offers some protection for the semiconductor substrate, maintaining the capacity for tunneling. Finally, a conductive layer is formed over the polysilicon layer, and the conductive layer combined with the polysilicon layer forms the select gate.

Abstract: A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bit line contacts, and each bit line contact is connected electrically to one of the first plugs. A cap layer is formed on top of the bit lines and spacers are formed on the sidewalls of the bit lines. The spacers are formed in such a way that they are linked near the bit line contact of every pair of neighboring bit lines. A planarized second insulation layer is formed over the substrate. Using the cap layers, the spacers and the second plugs as stopping points, an etching operation is carried out to form the lower electrode openings of capacitors and node contact openings.

Abstract: A method for forming a self-aligned contact structure is disclosed based on an HDP-CVD (High-Density Plasma-Chemical Vapor Deposition) process. Initially, after a polysilicon layer and a metal layer are deposited and patterned on a wafer to fabricate a gate stack, an HDP-CVD process is employed to form a deposition layer to cover the patterned layers and wafer. A building of sharp ridges occurs over the gate stack. Next, a spacer deposition layer is then conformally deposited to cover the HDP-CVD deposition layer. An anisotropically etch process is then performed to etch the spacer deposition layer, wherein at least portions of the spacer deposition layer still covers top of the gate stack. Another anisotropically etch process is then performed to form the required contacts on the wafer. Because the HDP-CVD deposition layer on the gate structure is thick enough to protect the gate stack from etching, it is unnecessary to form the cap layer as conventionally.

Abstract: A method of forming a crown-shaped capacitor. A dielectric layer, a stopping layer and a first material layer are sequentially formed over a substrate, and then a contact plug is formed through the three layers above the substrate. A first doped amorphous silicon layer and a second material layer are sequentially formed over the first material layer and the contact plug. The second material layer and the first doped amorphous silicon layer are patterned to form an opening that exposes the contact plug. A second doped amorphous silicon layer is formed over the exposed surface of the opening and above the second material layer on each side of the opening. The second doped amorphous silicon layer also covers the sidewalls of the second material layer and the first amorphous silicon layer to form doped amorphous silicon spacers. The second material layer and the first material layer are removed.

Abstract: A novel vertical poly load device in 4T SRAM and a method for fabricating the same are disclosed. The poly load structure is a vertical device formed on a buried contact. The poly load vertical device is constructed by forming a hollow in a planarized dielectric layer with a high temperature oxide layer on the walls of the hollow and with lightly doped n-type polysilicon in the hollow. The poly load is connected to the respective drain of the driver transistor through the buried contact and to the gate of the respective gate of the other driver transistor through a connecting line. The resistance of the poly load will increase, as the voltage of the buried contact becomes low thereby reducing the standby current.

Abstract: A method for fabricating landing pads for DRAM cells is disclosed. The method comprises following steps: At first, a substrate formed with isolation regions, periphery transistor region and a defined DRAM region are patterned so that an oxide layer on the defined DRAM region are removed to expose the source/drain region nitride caps, and nitride spacers. After a polysilicon layer is formed on all resulting surfaces, a photoresist pattern is subsequently formed on the polysilicon layer of the DRAM region so that the photoresist openings over the nitride cap are formed. Next, a conformal polymer layer of about 0.1 .mu.m in thickness is formed on all resulting surfaces so that a smaller polymer opening about 0.1 .mu.m size or beyond is formed in each of the photoresist openings. Finally, using the polymer layer as a mask and the nitride cap as a stopping layer, a polymer etching and a polysilicon etching are performed so that the landing pads are generated.

Abstract: A chemical-mechanical polishing station comprises a polishing table that has concentric rings. The rings are separated from each other by a small gap and all rings are capable of rotating in the same prescribed direction. A polishing pad is mounted on top of each ring, and a delivery tube is positioned at a distance above the polishing pads. The delivery tube further includes a tube handle and a tube surface, and the tube surface has a plurality of holes drilled in it for delivering slurry to the polishing pad surface. Each concentric ring of the polishing table is able to rotate such that all the rings have the same tangential polishing speed. Therefore a wafer surface can be more uniformly polished. Moreover, material having different density, roughness and chemical composition can be chosen to fabricate the polishing pads so that an even better polishing result can be obtained.

Abstract: The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.

Abstract: The method includes forming a first polysilicon on a substrate. Subsequently, a first dielectric layer is formed on the first polysilicon. A second polysilicon is pattern on the first dielectric layer, followed by depositing a second dielectric layer formed thereon. An etching is performed to etch the second dielectric layer, the second polysilicon layer through the first dielectric layer for generating an opening. An oxide layer is formed on the side-wall of the opening. A doped polysilicon layer is located at the lower portion of the opening. An undoped polysilicon layer is deposited on the second dielectric layer and refilled into the opening. An etching back is carried out to remove the layer over the second dielectric layer. A third polysilicon is patterned on the surface of the second dielectric layer. An isolation layer is deposited over the feature. A plurality of contact holes are generated in those isolation layers.

Abstract: A wafer-cleaning device comprises a looped belt forming an enclosed region and a pair of rollers. Each roller occupies one end inside the enclosed region. Furthermore, a supporting structure located inside the enclosed region not only supports the rollers, but also maintains some tension on the belt. Thus, one portion of the belt is flat. The supporting structure is capable of supporting a wafer as well. In addition, a wafer-rotating device can be installed next to the edge of a wafer so that the wafer can rotate in a prescribed direction while the wafer surface is cleaned.