Abstract: The DRAM capacitor fabrication in terms of damascene technology is disclosed. The processes are sequentially formed with word lines, landing pads and first interpoly dielectric (IPD1) layer. Thereafter, two approaching ways can be chosen. In the first embodiment, a thin nitride barrier is formed firstly, then the bit lines and IPD2 layer are formed. After that, a line mask pattern perpendicular to the bit lines are formed to serve as mask and use the nitride caps and nitride spacers as hard masks, then etching processes are implemented to form the storage nodes touching the landing pads. For increasing the storage node areas, the line masks are then descum in order to etch the IPD2 furthermore. The etch IPD2 process is using the nitride barrier as etching stopper. Then in-situ doped poly is deposited to form the bottom electrode. In the second embodiment, most of the processes are same as the first embodiment, except the thin nitride barrier process.

Abstract: A method of forming a capacitor. A substrate comprises a cell array area and a peripheral area. A dielectric layer is formed on the substrate. The covering layer is formed on the dielectric layer. The contact electrode is formed through the dielectric layer and the covering layer. The first oxide layer is formed over the substrate. A portion of the first oxide layer is removed to form an opening, which exposes the contact electrode. A conformal preserve layer is formed over the substrate. A second oxide layer is formed over the substrate. A portion of the second oxide layer in the cell array area is removed to form an opening, which exposes the contact electrode. A conformal first conductive layer is formed over the substrate to cover the second oxide layer and the opening. A third oxide layer is formed over the substrate to cover the first conductive layer and fill the opening.

Abstract: On a substrate, there is at least a first split gate and a second split gate. A dielectric layer is then formed on the substrate to cover the first split gate and the second split gate. The dielectric layer is patterned so that the dielectric layer covers at least a portion of the first split gate, a portion of the second split gate and a common source region between the first split gate and the second split gate. A polysilicon layer is formed on the dielectric layer. The polysilicon layer is then patterned.

Abstract: A method of fabricating a transistor. A first dielectric layer with a high dielectric constant is formed on a substrate. An oxide layer is formed on the first dielectric layer. A silicon nitride layer is formed on the oxide layer. The silicon nitride layer, the oxide layer, and the first dielectric layer are patterned to form a dummy gate structure. A spacer is formed on a sidewall of the dummy gate structure. The spacer and the dummy gate structure together form a dummy gate. An ion implantation step with the dummy gate serving as a mask and a thermal annealing step are performed to form a source region and a drain region on opposite sides of the dummy gate in the substrate. A second dielectric layer is formed next to the spacer. A top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure. The silicon nitride layer is removed. A nitridation process is performed to convert the oxide layer into a nitride layer.

Abstract: A split-gate source side injection flash EEPROM array structure and method of fabrication that utilizes the same polysilicon layer to form the control gate and the floating gate. Furthermore, there is a tunneling oxide layer underneath the floating gate, a gate oxide layer underneath the control gate, and that the tunneling oxide layer has a thickness smaller than the gate oxide layer. Since the control gate and the floating gate are formed on a silicon layer through the same patterning process, polysilicon spacers can be used to control the gap width between the control gate and the floating gate. Therefore, a reliable and reproducible flash cell array can be produced.

Abstract: A chemical-mechanical polishing station having a belt-operated conditioner. The belt-operated conditioner comprises a longitudinal main body, a belt sprinkled with hard particles, and a plurality of rollers. The belt wraps around the external edge of the longitudinal main body and is capable of rotating at a constant speed. The axles of the roller are parallel to each other. Furthermore, all the rollers are positioned within but touching the belt. Consequently, the rollers can rotate when they are driven by the belt. The hard particles sprinkled along the belt are used for scouring the polishing pad so that polishing pad surface can be reconditioned and any residual impurity particles can be removed. The belt-operated conditioner further includes a cleaning device. The cleaning device is used for removing any impurity particles clinging onto the belt when the conditioner is in operation.

Abstract: An alignment-marker structure and a method of forming the same in IC fabrication are provided. The alignment-marker structure is used for the purpose of assisting the precise alignment of a photomask used in photolithography on a wafer. In the fabrication process, a semiconductor substrate is prepared and then formed with a trench at a predefined location. A first conformal metallization layer is then formed over the substrate to a controlled thickness. Next, a sidewall-spacer structure is formed on the sidewall of the recessed portion of the first metallization layer. After this, a chemical-mechanical polishing (CMP) process is performed to polish away all the portions of the first metallization layer and the sidewall-spacer structure that lie over the top surface of the substrate. Finally, a second conformal metallization layer is formed over the substrate. Due to the conformal formation, the second metallization layer is formed with a recessed portion serving as the intended alignment mark.

Abstract: A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.

Abstract: A method for fabricating a stack capacitor with a hemi-spherical grain (HSG) structure is provided. A dielectric layer with a cave is first formed on a substrate. A conformal multi-layer amorphous silicon layer with low dopant concentration is formed over the substrate to cover the cave surface. An amorphous silicon layer with a sufficiently high dopant concentration is formed on the multi-layer amorphous silicon layer to fill the cave. After a planarization process, a remaining portion of the multi-layer amorphous silicon layer and the amorphous silicon layer form a storage node to fill the cave. The dielectric layer is removed to expose the storage node. A HSG is formed on the exposed surface of the storage node. An annealing process is performed to obtain a uniform dopant concentration. A dielectric thin film is formed over the storage node and the HSG layer. An upper electrode is formed to accomplish the stack capacitor.

Abstract: A method for manufacturing EPROM tunnel oxide cell having a damage-free source region. The method comprises the step of providing a substrate having a device region formed thereon, and then forming an ion-implanted region in the device area. Next, a gate oxide layer is formed over the substrate. Subsequently, a floating gate, a dielectric layer, a control gate and an oxide layer are sequentially formed above the substrate. This invention utilizes the implantation of a moderately heavy dose of ions into a device area prior to the formation of the gate oxide layer, so that a thicker gate oxide layer is formed above the source region. Hence, when the first polysilicon layer is etched in a subsequent self-aligned etching operation to establish the common source region, the thicker gate oxide layer can serve as a protective layer for the source region.

Abstract: A method for forming interconnection plugs comprising the steps of providing a substrate, then forming a dielectric layer having an opening that exposes a pad area for connection with other structures. Next, a glue layer is formed lining the opening and the dielectric layer. Subsequently, plug material is deposited into the opening to form a plug layer. This is followed by etching back the plug layer to a level higher than the glue layer that formed on the top of the dielectric layer. Thereafter, a metallic layer is formed over the plug layer, and a photoresist layer is then coated over the metallic layer. The metallic layer and the plug layer are then patterned by etching such that the plug layer is turned a plug. The characteristic of this invention lies in retaining a portion of the plug layer after the first etching such that the etched plug layer is at a level higher than the glue layer.