Patents Assigned to X-Fab Semiconductor Foundries, AG
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Patent number: 9627213Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.Type: GrantFiled: April 5, 2012Date of Patent: April 18, 2017Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Eng Gek Hee, Ka Siong Wisley Ung
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Patent number: 9559170Abstract: A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.Type: GrantFiled: March 1, 2012Date of Patent: January 31, 2017Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Patent number: 9543504Abstract: A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.Type: GrantFiled: October 21, 2015Date of Patent: January 10, 2017Assignees: MELEXIS TECHNOLOGIES NV, X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Christian Schott, Peter Hofmann
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Patent number: 9524963Abstract: A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.Type: GrantFiled: March 15, 2013Date of Patent: December 20, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Paul Ronald Stribley
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Patent number: 9496357Abstract: A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level.Type: GrantFiled: July 22, 2011Date of Patent: November 15, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Yong Hun Jeong, Bui Ngo Bong, Yen Thing Tay, Iliyana Manso
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Patent number: 9331211Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.Type: GrantFiled: August 28, 2009Date of Patent: May 3, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Paul Ronald Stribley, Soon Tat Kong
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Patent number: 9304104Abstract: A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.Type: GrantFiled: November 6, 2013Date of Patent: April 5, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Sang Sool Koo, Ling Gang Fang
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Patent number: 9293569Abstract: A bipolar junction transistor is provided with an emitter region, an oxide region, a base region and a collector region. The base region is located between the emitter region and the oxide region and has a junction with the emitter region and an interface with the oxide region. An at least partially conductive element such as metal or silicon is positioned to overlap with at least part of the junction between the base region and the emitter region, thereby forming a gate. The gate also overlaps with at least part of the interface between the base region and the oxide region. When a suitable bias voltage is applied to the gate, the gain of the transistor can be increased.Type: GrantFiled: October 15, 2013Date of Patent: March 22, 2016Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Brendan Toner, Xuezhou Cao, Fred Fang, Chuan Chien Tan
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Publication number: 20160056305Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.Type: ApplicationFiled: November 4, 2015Publication date: February 25, 2016Applicant: X-Fab Semiconductor Foundries AGInventors: Alexander Dietrich Holke, Deb Kumar Pal, Kia Yaw Kee, Yang Hao
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Patent number: 9224856Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.Type: GrantFiled: April 7, 2011Date of Patent: December 29, 2015Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Thomas Uhlig, Lutz Steinbeck
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Patent number: 9202937Abstract: A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.Type: GrantFiled: May 14, 2010Date of Patent: December 1, 2015Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Alexander Dietrich Hölke, Deb Kumar Pal, Kia Yaw Kee, Hao Yang
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Patent number: 9153716Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.Type: GrantFiled: October 20, 2014Date of Patent: October 6, 2015Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Daniel Gaebler, Wolfgang Einbrodt
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Patent number: 9070768Abstract: A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.Type: GrantFiled: February 15, 2010Date of Patent: June 30, 2015Assignees: X-FAB Semiconductor Foundries AG, Texas Instruments IncInventors: Ralf Lerner, Phil Hower, Gabriel Kittler, Klaus Schottmann
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Patent number: 9059110Abstract: A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.Type: GrantFiled: September 4, 2009Date of Patent: June 16, 2015Assignee: X-Fab Semiconductor Foundries AGInventors: Hyung Sun Yook, Tsui Ping Chu, Poh Ching Sim
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Publication number: 20150108559Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.Type: ApplicationFiled: April 5, 2012Publication date: April 23, 2015Applicant: X-FAB Semiconductor Foundries AGInventors: Eng Gek Hee, Ka Siong Wisley Ung
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Patent number: 8970016Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.Type: GrantFiled: June 1, 2012Date of Patent: March 3, 2015Assignee: X-FAB Semiconductor Foundries AGInventors: Marina Antoniou, Florin Udrea, Elizabeth Kho Ching Tee, Steven John Pilkington, Deb Kumar Pal, Alexander Dietrich Hölke
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Patent number: 8921945Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 ?m. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.Type: GrantFiled: June 15, 2009Date of Patent: December 30, 2014Assignee: X-Fab Semiconductor Foundries AGInventor: Ralf Lerner
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Publication number: 20140367796Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.Type: ApplicationFiled: November 15, 2011Publication date: December 18, 2014Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Brendan Toner, Tsui Ping Chu, Foo Sen Liew
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Patent number: 8901614Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.Type: GrantFiled: May 19, 2009Date of Patent: December 2, 2014Assignee: X-Fab Semiconductor Foundries AGInventors: Michael Stoisiek, Michael Gross
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Patent number: 8865553Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.Type: GrantFiled: September 30, 2009Date of Patent: October 21, 2014Assignee: X-Fab Semiconductor Foundries AGInventors: Wolfgang Einbrodt, Daniel Gaebler