Abstract: The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29).

Abstract: A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.

Abstract: A test structure and a process for the electromigration test of integrated circuits is suggested, in which metallization planes consisting of strip conductors of a usual thickness (11) are connected with metallization planes consisting of substantially thicker strip conductors (12) as they are required for the connection of components of higher performance.

Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.

Abstract: A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: A semiconductor device comprising: at least one strained semiconductor layer to change the probability of an electron tunnelling from a first area to a second area.

Abstract: The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.

Abstract: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realization of MEMS structures of SOI wafers. A reliable dielectric insulation of adjacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches. The end portions of the trench fill that are freed from the surrounding silicon by etching are free of conductive not completely removed silicon strips in the recess including the active sensor structure. This is accomplished by slanted wall of isolation trenches. Additionally, the trench fill should be removable at the transition area in an efficient manner. The technological realization does not require specific additional process steps.

Abstract: A method of manufacturing an Organic Light Emitting Diode (OLED). A substrate (101) is provided, and a plurality of pixel electrodes (102) is formed on the substrate resulting in at least one gap (105) between two adjacent pixel electrodes. A dielectric material (103) is deposited in the gap. The resulting structure is subjected to a process which ensures that at least a portion of the surface of the pixel electrodes is not covered by the dielectric material. At least the portion of the surface of the pixel electrodes is covered with a layer of an organic compound so as to form the OLED.

Abstract: In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

Abstract: A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor (42) and a second capacitor (44) that one connected in an anti-parallel manner. The insulating layer (18) of the first capacitor comprises silicon nitride and the insulating layer (16) of the second capacitor comprises silicon dioxide.

Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 ?m, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a?) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract: A method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method for aligning the electronic CMOS structure may include forming alignment marks in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer, which includes the structure to be buried. The alignment marks may be formed on the edge of the semiconductor wafer. The method for aligning the electronic CMOS structure may include providing a cover wafer with first thinned portions of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks.

Abstract: A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.

Abstract: A bipolar junction transistor is provided with an emitter region, an oxide region, a base region and a collector region. The base region is located between the emitter region and the oxide region and has a junction with the emitter region and an interface with the oxide region. An at least partially conductive element such as metal or silicon is positioned to overlap with at least part of the junction between the base region and the emitter region, thereby forming a gate. The gate also overlaps with at least part of the interface between the base region and the oxide region. When a suitable bias voltage is applied to the gate, the gain of the transistor can be increased.

Abstract: A system and a method for testing the ESD behavior, wherein a circuit (7) is automatically tested at circuit diagram level in that technology-specific ESD data is provided in database (2) for each circuit component present in the circuit, without requiring complex circuit simulations, for example based on front end or back end data, by taking into account the layout.

Abstract: An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.

Abstract: The invention relates to a vertical Hall sensor integrated in a semiconductor chip and a method for the production thereof. The vertical Hall sensor has an electrically conductive well of a first conductivity type, which is embedded in an electrically conductive region of a second conductivity type. The electrical contacts are arranged along a straight line on a planar surface of the electrically conductive well. The electrically conductive well is generated by means of high-energy ion implantation and subsequent heating, so that it has a doping profile which either has a maximum which is located at a depth T1 from the planar surface of the electrically conductive well, or is essentially constant up to a depth T2.