Abstract: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then RIE etched to initially remove the oxide layer from the wafer surface with continued etching to remove the oxide layers in upper trench portions to define later sealing portions of the voids or to displace the first bottlenecks downward to define further bottlenecks. A second SiO2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.

Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.

Abstract: A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate form a diode. The semiconductor device further includes an inductor on or above the semiconductor material, and a pattern in the semiconductor material for reducing eddy currents. The pattern includes a doped semiconductor material of the first doping polarity and a least one trench within the doped semiconductor material of the first doping polarity, wherein, at least at a depth at which the trench is closest to the inductor, the doped semiconductor material of the first doping polarity fully surrounds the trench so that, at least at the depth, the trench does not touch the doped semiconductor material of the second doping polarity.

Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 ?m. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.

Abstract: A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.

Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

Abstract: A method in which an oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor).

Abstract: A system and a method for testing the ESD behaviour, wherein a circuit (7) is automatically tested at circuit diagram level in that technology-specific ESD data is provided in database (2) for each circuit component present in the circuit, without requiring complex circuit simulations, for example based on front end or back end data, by taking into account the layout.

Abstract: Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.

Abstract: For bonding a donor wafer (1) and a system wafer (9) an edge bead (3) of an epitaxial layer (2) on the donor wafer is flattened or completely removed by etching so that a reliable contact after bonding up to the edge region (5, 6) is possible. The etching mask is produced by means of a resist layer (4) as well as by means of removal of resist at the edge, free exposure and developing without a special photomask.

Abstract: Disclosed is a semiconductor structure for producing a handle wafer contact in trench insulated SOI discs which may be used as a deep contact (7, 6, 30?) to the handle wafer (1) of a thick SOI disc as well as for a trench insulation (40). Therein, the same method steps are used for both structures which are used as deep contact to the handle wafer of the thick SOI disc as well as trench insulation.

Abstract: The invention relates to a method and a through-vapor mask for depositing layers in a structured manner by means of a specially designed coating mask which has structures that accurately fit into complementary alignment structures of the microsystem wafer to be coated in a structured manner such that the mask and the wafer can be accurately aligned relative to one another. Very precisely defined portions on the microsystem wafer are coated through holes in the coating mask, e.g. by mans of sputtering, CVD, or to evaporation processes.

Abstract: In an integrated circuit, a light sensitive area is protected against radiation by arranging a light blocking layer sequence (504) on top of the light sensitive area. The light blocking layer sequence comprises one or several metal layers (504a) and a silicon layer (503b, 1) for the purpose of absorption. A moth eye structure is provided on the silicon layer. Thereby, a radiation incident by reflection is minimized in such a way that also stray light can effectively be kept from the light sensitive area below the light blocking layer sequence (504).

Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.

Abstract: The invention relates to a method for selective material deposition for sensitive structures in micro systems technology for producing mechanical adjustment structures (6, 5) for a vapour penetration mask (8), the adjustment structures on the component disc (7) and the mask being created using the same structuring method. Complementary adjustment structures can be produced thereon with a very high degree of precision. KOH etching in silicon can be used in order to create equally inclined flanks (2, 2a) in a depression and a complementary protrusion.

Abstract: A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).

Abstract: A device comprises a substrate (22); a first MiM capacitor (10,20,11) disposed over the substrate; and a second MiM capacitor (10?,20?,11) disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (10,10?) of the CMOS process as one plate and a thinner conductive layer (11,11?) as the second plate, with an insulating layer (20,20?) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor.

Abstract: The invention relates to a method for producing semiconductor substrates by bonding. The aim of said method is to reduce the non-usable edge region on the bonded wafer component and to improve the edge geometry of the wafer composite. This is achieved by a method for joining two semiconductor wafers using a semiconductor wafer bonding process. The surfaces of the two semiconductor wafers that are to be bonded are provided with a border or edge geometry that has a special short front-end facet. After the bonding process, one of the two wafers is ablated to obtain an edge region that is as devoid as possible of defects and a usable wafer surface that is as large as possible.

Abstract: The present invention provides a method for fabricating a MOS transistor (100) with suppression of edge transistor effect. In one embodiment of an NMOS, an elongate implant limb (110, HOa, 114) extends from each of two sidewalls (14a, 14b) of a p-type well (14) to partially wrap around each respective longitudinal end of the gate (20) and to overlay a portion thereof. In another embodiment, the elongate implant limb (110, 110a) extends into the drain/source drift region (32, 42). The NMOS transistor (100) thus fabricated allows the NMOS transistor to operate at relatively high voltages with reduced drain leakage current but with no additional masks or process time in the process integration.

Abstract: The invention concerns semiconductor latches capable of memorizing any programmed information even after power supply has been removed. Used is a ?m BiCMOS EPROM process but it is applicable in any other process having hot electron injection devices like EPROM, Flash EEPROM.