Abstract: The invention refers to an efficient process for selectively rendering a semiconductor surface antireflective which is part of integrated circuits. The antireflective effect is based interference effects of a simple layer or a layer system. For example, an oxide layer and super-imposed silicon nitride layer form the system, wherein the silicon nitride layer is deposited in an earlier phase of the fabrication of the integrated circuit as a protective layer (“silicide block layer”) and also serves as an etch stop layer for the optical window.

Abstract: The invention relates to processes for the production and elements (components) with a nanostructure (2; 4, 4a) for improving the optical behavior of components and devices and/or for improving the behavior of sensors by enlarging the active surface area. The nanostructure (2) is produced in a self-masking fashion by means of RIE etching and its material composition can be modified and it can be provided with suitable cover layers.

Abstract: A CMOS circuit comprises at least one high voltage transistor (having gate and drain operating voltages of greater than 8V) and at least one high frequency capable transistor (having a maximum switching frequency of between 100 MHz and 1000 GHz) wherein said transistors are integrated on the same semiconductor substrate so as to allow the simple integration of high voltage circuits and RF (radio frequency) CMOS circuits on the same integrated circuit.

Abstract: The invention relates to a method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).

Abstract: A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.

Abstract: An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.

Abstract: The invention relates to isolation trenches having a high aspect ratio for trench-insulated smart power technologies in Silicon On Insulator (SOI) silicon wafers. The specific geometric layout of the intersections and junctions of the isolation trenches allows error rate reduction and simplification of manufacture.

Abstract: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.

Abstract: The invention relates to methods and devices comprising a nanostructure (2;4,4a) for improving the optical behavior of components and apparatuses and/or improving the behavior of sensors by increasing the active surface area. The nanostructure (2) is produced by means of a special RIE etching process, can be modified regarding the composition of the materials thereof, and can be provided with adequate coatings. The amount of material used for the base layer (3) can be reduced by supplying a buffer layer (406). Many applications are disclosed.

Abstract: A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the opposite polarity and also comprises silicon containing germanium at least at the bottom of the base (13). An emitter is formed at the top of the base (13) and comprises polysilicon doped to have the same polarity as the collector (12).

Abstract: The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In addition, the costs of the material removal process should be reduced by minimizing the complexity of monitoring, as well as by reducing the amount of resulting refuse. To this end, the invention provides a test structure (4, 5, 6, 7, 8, 9) comprised of a systematic row of a number of different depth trenches that are made in the (active) wafer (2). A thickness (h6; h7) of the active wafer (2) desired during material removal, particularly during a polishing, corresponds to the depth (t6; t7) of a reference trench (6; 7) of the trenches of the test structure, said reference trench (6) being surrounded by flatter and deeper trenches (5, 7).

Abstract: A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate form a diode. The semiconductor device further includes an inductor on or above the semiconductor material, and a pattern in the semiconductor material for reducing eddy currents. The pattern includes a doped semiconductor material of the first doping polarity and a least one trench within the doped semiconductor material of the first doping polarity, wherein, at least at a depth at which the trench is closest to the inductor, the doped semiconductor material of the first doping polarity fully surrounds the trench so that, at least at the depth, the trench does not touch the doped semiconductor material of the second doping polarity.

Abstract: The invention provides a simple to implement and reliable recognition of the moment at which insulation trenches reach the buried insulating layer during an etch process. The technological reliability during the etching of such trenches is increased, the production of refuse is prevented, and costs are reduced. To these ends, the invention provides a test structure for verifying an insulation trench etching in an SOI wafer. After an etching o insulation trenches, the test structure has a row of connected islands, whereby each island is surrounded by a trench. This trench has a different width form island to island (A,B; B,C) while including a trench width that appears the form of an insulation trench in an active circuit. A section of the surrounding trench (a,b) of each island (A,B) forms a common piece with the trench of adjacent islands. The respective section has, in the inner islands, the width of the adjacent trench having the next larger or the next smaller measure of width in the row.

Abstract: Methods and optical devices are proposed, which comprise a nanostructure (4) on a curved surface so that a broadband antireflective characteristic is obtained.

Abstract: A method and device for determining the thicknesses of semiconductor membranes uses electrical measurements. Energy is coupled into the membrane in a defined manner and the membrane thickness is determined from the distribution or diffusion of the energy. A change of state of the membrane is detected by measuring electroconductivity of measuring resistances at least one of which is on the membrane. The electroconductivity varies according to the temperature and the mechanical strain of the membrane, which both depend on the thickness of the membrane.

Abstract: The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is formed by combining a low doped first p-epitaxial layer, which has maximum thickness and doping concentration, placed upon a particularly high doped p substrate, with a low doped second n? epitaxial layer that borders the first layer, and n+ cathode of the pin photodiode being integrated into the second layer. The p areas delimit the second n epitaxial layer in a latent direction while another anode connecting area of the pin diode is provided on the rear face in addition to the anode connection.

Abstract: A process and a test structure for testing the hermeticity of bond connections are described. Points are provided on the wafer pair to be connected, at which hermetically closed cavities are additionally formed upon the connection of the wafers, e.g., as they are customary in microelectromechanical systems (MEMS). A pressure sensor structure and a structure are located in these cavities by means of which the internal pressure of the cavity can be changed from the outside, such as metal webs with narrowed cross-section which are built up in accordance with the principle of a fuse and, upon the generation of a current flow, melt or evaporate via the electrodes that lead towards the outside of the cavity. The chronological change of the changed internal pressure is tracked in a measuring fashion.

Abstract: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12) to be patterned and a rear side (13). The substrate is oxidized in two steps. In a first step the rear side (13) is covered by a layer (4) that inhibits or hampers the oxidation. During a second step of the oxidation the oxidation-hampering layer (4) is no longer present. During both steps an oxide thickness is obtained on the front side (12) that is greater than an oxide thickness obtained on the rear side (13).

Abstract: The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches (10, 10?) in critical areas (at intersections and junctions) are improved. Flattened and/or rounded off corner areas (10a, 10b) of the semiconductor regions to be insulated are produced, the etching and filling behavior being adjusted to be similar to that in the areas outside the critical areas, a center island (18, 18?) being provided for adapting the effective trench width in the critical areas of transition. The isolation trench structure is suitable for semiconductor arrangements (smart power applications) in which large voltage differences occur between the regions (12, 12?) to be electrically insulated from each other and the corresponding components. Power components can be integrated on the same chip together with small-signal elements.

Abstract: The invention relates to a method and arrangement for carrying out the nondestructive determination of the connection quality of bonded wafers (1, 8) in order to verify the connection strength. The fact that an unbonded region (9) forms around a raised or recessed structure (3) on at least one of the connecting surfaces is made use of. The extension of the unbonded region is a measure of the strength of the wafer connection and is electrically determined by staggered contacts (5, 4) that, with the formation of the bond connection, close, only in part, via a contact strip (10).