Abstract: Processing of a neural network specification includes gathering first layers of a neural network graph into groups of layers based on profiled compute times of the layers and equalized compute times between the groups. Each group is a subgraph of one or more of the layers of the neural network. The neural network graph is compiled into instructions for pipelined execution of the neural network graph by compute circuits. The compiling includes designating, for each first subgraph of the subgraphs having output activations that are input activations of a second subgraph of the subgraphs, operations of the first subgraph to be performed by a first compute circuit and operations of the second subgraph to be performed by a second compute circuit. The compute circuits are configured to execute the instructions.

Abstract: One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

Abstract: A system can include a microprocessor having a prefetch queue including a plurality of slots configured to store program counter values (PCVs) and instructions, a pipeline configured to receive instructions from the prefetch queue, and a select circuit coupled to the prefetch queue. The select circuit may selectively freeze a first slot of the plurality of slots and selectively output a frozen PCV and a frozen instruction from the first slot while frozen. The microprocessor can include write logic coupled to the prefetch queue and a comparator circuit coupled to the prefetch queue and the select circuit. The write logic may load data into unfrozen slots of the prefetch queue. The comparator circuit may compare a target PCV with the frozen PCV to determine a match. The select circuit indicates, to the pipeline, whether the frozen instruction is valid based on the comparing.

Abstract: Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

Abstract: Examples described herein generally relate to wafer testing and structures implemented on a wafer for wafer testing. In an example method for testing a wafer, power is applied to a first pad in a test site (TS) region on the wafer. The TS region is electrically connected to a device under test (DUT) region on the wafer. The DUT region includes a DUT. The TS region and DUT region are in a first and second scribe line, respectively, on the wafer. A third scribe line is disposed on the wafer between the TS region and the DUT region. A signal is detected from a second pad in the TS region on the wafer. The signal is at least in part a response of the DUT to the power applied to the first pad.

Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.

Abstract: Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through Kby determining respective sets of intermediate z-limbs 0 through K- 1 for r-limbs i for i = 0 to K - 1, and summing corresponding ones of the intermediate z-limbs of sets i through K - 1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K - 1 of set 0 as products of r-limb 0 and a-limbs 0 through K - 1, and for the remaining r-limbs determines intermediate z-limbs using different combinations of a-limbs, r-limbs, modulus, and d-limbs. A modulo circuit computes G as (most significant M bits of Z* m) + (least significant Q bits of Z, wherein M is a number of bits by which a number of bits of Z exceeds N, and Q is equal to M + ceil (log2 m), and increases G by m if bits Q through N - 1 of Z all having bit value one, and G ? 2Q - m.

Abstract: Training of a machine learning model used to infer estimated delays of circuit routes during placement and routing of a circuit design. Training can include selecting sample pairs of source pins and destination pins of an integrated circuit (IC) device, and determining respective delays of shortest paths that connect the source pins to the destination pins of the sample pairs based on a resistance-capacitance model of wires that form the shortest paths on the IC device. Respective sets of features are determined for the shortest paths, and the model is trained using the respective sets of features and the respective delays as labels. The machine learning model can be provided to an electronic design automation tool for estimating delays.

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Abstract: Examples herein describe an acceleration framework that includes a hybrid congestion control (CC) engine where some components are implemented in software (e.g., a CC algorithm) while other components are implemented in hardware (e.g., measurement and enforcement modules and a flexible processing unit). The hardware components can be designed to provide measurements that can be used by multiple different types of CC algorithms. Depending on which CC algorithms are currently enabled, the hardware components can be programmed to perform measurement, processing, and enforcement tasks, thereby freeing the CPUs in the host to perform other tasks. In this manner, the hybrid CC engine can have the flexibility of a pure software CC algorithm with the advantage of performing many of the operations associated with the CC algorithm in hardware.

Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

Abstract: A method for measuring asynchronous timestamp requests includes receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (“TOD”) clock, and calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first TOD clock interval. The method further includes adding the TS correction to the reference point of the first interval of the TOD clock, and outputting the corrected TS to the client device.

Abstract: Transformer based voltage controlled oscillator circuitry for phase-locked loop circuitry includes upper band circuitry and lower band circuitry. The upper band circuitry operates in a first frequency range and includes a first capacitor array having a variable capacitance. The lower band circuitry operates in a second frequency range and includes a second capacitor array having a variable capacitance. The first frequency range higher than the second frequency range. In a first operating mode, the first capacitor array has a first capacitance value and the second capacitor array has a second capacitance value. In a second operating mode, the second capacitor array has a third capacitance value different than the second capacitance value.

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.

Abstract: Disclosed approaches for accumulating pre-carry data include initializing hold sum to a sum of a LSB of the first pre-carry word of an input stream and an MSB of a second pre-carry word by a pre-carry processing circuit. For successive pre-carry words, the LSB of pre-carry word i and the MSB of pre-carry word i+1 are summed into a next sum. An FFcount is incremented by an adder circuit if the LSB of the next sum is equal to 0xFF. If the LSB of the next sum is not equal to 0xFF, the pre-carry processing circuit outputs either: the hold sum followed by FFcount consecutive 0xFF values, if the MSB of the next sum is equal to 0x00, or the hold sum plus one, followed by FFcount consecutive 0x00 values, if the MSB of the next sum is not equal to 0x00. If the LSB of the next sum is not equal to 0xFF, the hold sum is updated with the LSB of the next sum, and the FFcount is reset to 0. Processing repeats for successive pre-carry words in the stream.

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.