Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

Abstract: Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.

Abstract: Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according to the schedule.

Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

Abstract: An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.

Abstract: A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.

Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.

Abstract: An example method of flow control between remote hosts and a target system over a front-end fabric, the target system including a nonvolatile memory (NVM) subsystem coupled to a back end fabric having a different transport than the front-end fabric is described. The method includes receiving commands from the remote hosts at a controller in the target system for the NVM subsystem. The method further includes storing the commands in a first-in-first-out (FIFO) shared among the remote hosts and implemented in memory of the target system. The method further includes updating virtual submission queues for the remote hosts based on the commands stored in the FIFO. The method further includes providing the commands to the NVM subsystem from the FIFO.

Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

Abstract: A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is retrieved and is used until the analytics device has caught up.

Abstract: Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The overlay is synthesizable to implement the ML primitive on the target hardware. The overlay can be scheduled for operation within the target hardware as part of an ML design including the ML primitive.

Abstract: A computer-based visualization and refactoring system is capable of analyzing a computer program to determine computation tasks of the computer program and channels linking the computation tasks. The system generates, in a memory of computer hardware, a dataflow graph having nodes representing the computation tasks and edges representing the channels. The edges connect the nodes. Source code representations of the computation tasks are determined. Execution metrics of the computer program are determined. The nodes of the dataflow graph are annotated with the source code representations and the nodes and/or the edges are annotated with the execution metrics. The dataflow graph is displayed on a display device as annotated.

Abstract: An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

Abstract: A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.