Abstract: An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

Abstract: Implementing a circuit design within an integrated circuit can include converting the circuit design, specified in a hardware description language, into a data flow graph and creating range set data structures in a memory. The range set data structures correspond to nodes of the data flow graph. Each range set data structure can be initialized with a range of values the corresponding node can take as specified by the circuit design. The method can include determining actual values the nodes are capable of taking by propagating the values through the data flow graph. The range set data structures are updated to store the actual values for the corresponding nodes. The method also can include modifying a selected node of the data flow graph based on the actual values stored in the range set data structure of the selected node and semantics of the selected node.

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

Abstract: Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

Abstract: A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel channel for transmission over a serial link to a second IC. Each transceiver circuit includes a receive channel configured to depacketize data received from the serial link from the second IC. The serial link is asynchronous to each of parallel channel coupled to the first bridge circuit.

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The blockchain may include multiple peer-nodes, each of which contains standard software running on a server or container. Instead of validating a block of transactions using software, the hardware accelerator can validate the transactions in a fraction of the time. The peer-node software then gathers the validation results from the hardware accelerator and combines the results with received block data to derive the block which is committed to the stored ledger.

Abstract: Examples herein describe a programmable traffic management engine that includes both programmable and non-programmable hardware components. The non-programmable hardware components are used to generate features that can then be used to perform different traffic management algorithms. Depending on which traffic management algorithm the PTM engine is configured to do, the PTM engine may use a subset (or all) of the features to perform the algorithm. The programmable hardware components in the PTM engine are programmable (e.g., customizable) by the user to perform a selected algorithm using some or all of the features provided by the non-programmable hardware components.

Abstract: Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from the respective memory bank. A second switching circuit (304) routes tuples based on row indices of the tuples. Each tuple includes a product output by the one of the N multipliers and a row index output by an output port of the first switching circuit. N accumulator circuits (307) sum products of tuples having equal row indices.

Abstract: Implementing an application can include generating, from the application, a compact data flow graph (DFG) including load nodes, inserting, in the compact DFG, a plurality of virtual buffer nodes (VBNs) for each of a plurality of buffers of a data processing engine (DPE) array to be allocated to nets of the application, and, forming groups of one or more load nodes of the compact DFG based on shared buffer requirements of the loads on a per net basis. Virtual driver nodes (VDNs) that map to drivers of nets can be added to the compact DFG, where each group of the compact DFG is driven by a dedicated VDN. Connections between VDNs and load nodes through selected ones of the VBNs are created according to a plurality of constraints. The plurality of buffers are allocated to the nets based on the compact DFG as connected.

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

Abstract: Embodiments herein describe using software or firmware to manage the device capability list of a PCIe device. That is, rather than relying on pure hardware to advertise the capabilities of a PCIe device, the embodiments herein permit software or firmware executing on a processor in the PCIe device to manage read and write requests associated with discovering the capabilities of the device and configuring the device.

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.