Abstract: A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.

Abstract: In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

Abstract: Examples described herein provide a wearout card and a method for using the wearout card. The wearout card generally includes a first set of connectors configured to connect the testing apparatus to a testing controller, and a second set of connectors configured to connect the testing apparatus to a device under test (DUT). The wearout card can also include a memory configured to store identifying information of the testing apparatus and a use counter indicating a number of times different DUTs have been connected to the second set of connectors.

Abstract: Cross-coupling of switched-capacitor output common-mode feedback capacitors in dynamic residue amplifiers is provided via a cross-coupled amplifier, comprising: a current source connected to a first node; a feedback capacitor connected to the first node and a second node; a feedback resistor connected between the second node and ground; an amplifier having an input connected to the second node; a gain transistor having: a drain connected to the first node; a source connected to ground; and a gate connected to an output of the amplifier; and a load capacitor connected to the first node and ground.

Abstract: Anti-spoofing of a deep learning neural network may include receiving, by an artificial neural network implemented in hardware, an image and multi-dimensional spatial frequency data for the image. The artificial neural network is trained using training images and multi-dimensional spatial frequency data for the training images. Using the artificial neural network, a classification for an object in an image is determined based on the image and the multi-dimensional spatial frequency data for the image.

Abstract: Embodiments herein describe placing a filter network at one of the inputs of the comparator to avoid injecting unequal amounts of kickback noise into the inputs of the comparator. In one embodiment, the filter network matches the impedance seen at the inputs of the comparator. As a result, the amount of kickback noise is essentially equal at the inputs even though the input signals may be at different frequencies. Thus, the kickback noise is essentially cancelled out so that this noise has little to no impact on the output of the comparator.

Abstract: Examples herein relate to devices that include a strobe tree circuit for capturing data using a memory-sourced strobe. In an example, a device includes a data capture path including first and second flip-flops, and a strobe tree including a comparator and first and second multiplexers. The comparator is configured to output complementary signals on first and second output nodes. First and second selection input nodes of the first multiplexer are connected to the first and second output nodes of the comparator, respectively. First and second selection input nodes of the second multiplexer are connected to the second and first output nodes of the comparator, respectively. The read strobe tree is configured to provide first and second signals output from the first and second multiplexers to first and second nodes, respectively. Clock input nodes of the first and second flip-flops are connected to the first and second nodes, respectively.

Abstract: Examples described herein provide a radio frequency circuit. The radio frequency circuit includes a controller; a parameter estimator circuit; a capture circuit; and a pre-distorter circuit. The pre-distorter generally includes one or more nonlinear filter circuits and configurable hardware circuitry. Each of the one or more the nonlinear filter circuits includes: adder(s); multiplier(s); and memories coupled to at least one of the adder(s) and the multiplier(s); where the configurable hardware circuitry is configured to distort one or more input signals by directing the one or more input signals along a path through the one or more adders, the one or more multipliers, and the one or more memories and by distorting the one or input signals using the nonlinear parameters stored in the one or more memories as the one or more input signals travels the path.

Abstract: A heat exchanger and an antenna assembly having the same are described herein that enable a compact antenna design with good thermal management. In one example, a heat exchanger is provided that includes tube-shaped body. A main cooling volume is formed between the top and bottom surfaces proximate to the outside wall. The main cooling volume has an inlet formed through the top surface and an outlet formed through the bottom surface. A return volume is formed adjacent the inside diameter wall and is circumscribed by the main cooling volume. The return volume has an outlet formed through the top surface and an inlet formed through the bottom surface. One or more exterior fins are coupled to an exterior side of the outside wall. A plurality of fins extend into the main cooling volume. A plurality of inner fins extend into a passage from the inside diameter wall.

Abstract: The present invention provides a massive MIMO antenna for wireless communication, the massive MIMO antenna comprising a plurality of antenna elements configured to receive upstream wireless signals and to transmit downstream wireless signals, the antenna elements being arranged in a matrix-like arrangement comprising rows and/or columns of antenna elements, a plurality of transceivers, each coupled to at least one of the antenna elements, and a control unit configured to selectively activate and/or deactivate specific ones of the transceivers. In addition, the present invention provides a respective method for operating a massive MIMO antenna.

Abstract: Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.

Abstract: A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.

Abstract: An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

Abstract: The embodiments herein describe a virtualization framework for cache coherent accelerators where the framework incorporates a layered approach for accelerators in their interactions between a cache coherent protocol layer and the functions performed by the accelerator. In one embodiment, the virtualization framework includes a first layer containing the different instances of accelerator functions (AFs), a second layer containing accelerator function engines (AFE) in each of the AFs, and a third layer containing accelerator function threads (AFTs) in each of the AFEs. Partitioning the hardware circuitry using multiple layers in the virtualization framework allows the accelerator to be quickly re-provisioned in response to requests made by guest operation systems or virtual machines executing in a host. Further, using the layers to partition the hardware permits the host to re-provision sub-portions of the accelerator while the remaining portions of the accelerator continue to operate as normal.

Abstract: Some examples described herein relate to a boot image file. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to compile an application to generate a boot image file. The boot image file is capable of being loaded onto and executed by a programmable device that comprises data processing engines (DPEs). The boot image file has a format comprising a platform loader and manager (PLM) and partitions. The PLM comprises code capable of being executed by a controller of the programmable device to load the partitions onto the programmable device. Each of the partitions comprises a bitstream, executable code, data, or a combination thereof. The partitions collectively include a single global partition that comprises DPE partitions that are capable of being loaded onto one or more of the DPEs.

Abstract: Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.

Abstract: Lossy tensor compression and decompression circuits compress and decompress tensor elements based on the values of neighboring tensor elements. The lossy compression circuit scales each decompressed tensor element of a tile by a scaling factor that is based on the maximum value that can be represented by the number of bits used to represent a compressed tensor element, and the greatest value and least value of the tensor elements of the tile. The lossy decompression circuit performs the inverse of the lossy compression. The compression circuit and decompression circuit have parallel multiplier circuits and parallel adder circuits to perform the lossy compression and lossy decompression, respectively.

Abstract: Modifying a flow table for a network accelerator can include, in response to determining that a flow table of a network accelerator does not include any rules corresponding to first packet data of a first flow received from a network, forwarding the first packet data to a host computer. Subsequent to the flow table being updated to include a new rule for the first flow, for second packet data of the first flow received from the network, the second packet data can be processed using the new rule. The second packet data can be queued. In response to receiving the first packet data from the host computer, the first packet data can be processed using the new rule. The processed packet data can be forwarded to a destination port followed by the queued second packet data.

Abstract: Embodiments herein describe an FFT that can bypass one or more stages when processing smaller frames. For example, when all the stages in the FFT are active, the FFT can process up to a maximum supported point size. However, the particular application may only every send smaller sized frames to the FFT. Instead of unnecessarily passing these frames through the beginning stages of the FFT (which adds latency and consumes power), the embodiments herein can bypass the unneeded stages which reduces the maximum point size the FFT can process but saves power and reduces latency. For example, the FFT can have selection circuitry (e.g., multiplexers) disposed between each stage that permits the input data to either bypass the previous stage(s) or the subsequent stage(s), depending on the architecture of the FFT. The bypassed stages can then be deactivated to conserve power.