Abstract: An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.

Abstract: An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells.

Abstract: The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal.

Abstract: A suspend mode is provided that can be asserted using an Internal Configuration Access Port (ICAP) of an integrated circuit such as a Field Programmable Gate Array (FPGA), as supposed to a dedicated external suspend pin typically accessed by a device external to the FPGA. The ICAP is designed to assert the suspend mode through a configuration block to maintain the state of the configuration memory array while lowering power, in a similar manner to when an external suspend pin is accessed. Internal circuits can, thus, be used to assert a suspend mode through the ICAP.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: A clock data recovery module and a method of operation thereof are described. In an embodiment, a data stream is received. Transitions in the data stream are detected to provide phase signaling for indicating phase relationships to the transitions detected. A lock detector receives the phase signaling. The lock detector accumulates phase information from the phase signaling and temporarily stores an accumulated total of the phase information representative of a code change, and the lock detector determines whether the code change is within a set range over a time period and resets the accumulated total at a conclusion of the time period.

Abstract: A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.

Abstract: In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.

Abstract: Method and apparatus for concatenated and interleaved turbo product code decoding are described. The turbo encoder include a plurality of decoders coupled to receive first portion of data, a processor coupled to receive second portion of the data, and a controller providing a plurality of control signals coupled to the plurality of decoders and the processor. A control signal of the plurality of control signals coupled to the processor when enabled configures the processor to pre-calculate the second portion of the data, where the second portion of the data is trellis termination data.

Abstract: Architecture of a digital signal processing engine and method for digital signal processing therewith are described. Instruction memory stores an instruction which has at least one opcode which is selected from a group consisting of a control opcode, a digital signal processing (DSP) opcode, and a memory opcode. A digital signal processing engine includes a controller for receiving the control opcode, a DSP core for receiving the DSP opcode, and a memory interface for receiving the memory opcode. The controller, the digital signal processing core, and the memory interface are separate pipelines at least two of which have different numbers of stages. The controller may include an arithmetic logic unit, a base address regfile, and a branch/decode circuit.

Abstract: A configurable memory map interface coupled to a circuit element having input/output ports is disclosed. The configurable memory map interface comprises an input coupled to receive an address enabling reading from or writing to the circuit element; a memory storing enable signal parameters, the enable signal parameters controlling timing of enable signals for the reading from or the writing to the circuit element; and an enable signal generator generating the enable signals enabling the reading from or the writing to the circuit element based upon the enable signal parameters stored in the memory. A method of implementing a configurable memory map interface is also disclosed.

Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.

Abstract: A circuit for receiving a sample of an input signal to be used to calculate parameters for a predistortion circuit in an integrated circuit is described. The circuit comprises a power measurement circuit coupled to receive the input signal; a first port of a dual port random access memory for receiving data associated with power of the input signal over a predetermined period of time; and a second port of a dual port random access memory for generating the data associated with the power of the input signal stored over the predetermined period of time. A method of receiving a sample of an input signal to be used to calculate parameters for a predistortion circuit in an integrated circuit is also described.

Abstract: Efficiency is improved for device drivers. A first library is input that includes a first version of the device drivers. First metadata is input that specifies the devices of the computing arrangement and associates each device with the first version of a corresponding device driver. The first version of the corresponding device driver for each device is transformed into a second version of the corresponding device driver. The first version of the corresponding device driver indirectly accesses the device and the second version of the corresponding device driver directly accesses the device. A second library is output including the second version of the corresponding device driver for each device.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: In one embodiment, a method for restricting use of an integrated circuit (IC) is provided. A write-once memory of a programmable IC contains a first die-specific performance grade indicator. In response to receiving an input code having a second die-specific performance grade indicator with a value indicating a level of performance greater than or equal to a level of performance indicated by the first die-specific performance grade indicator, enabling operation of the IC. In response to receiving a configuration bitstream having the second die-specific performance grade indicator with a value indicating a level of performance less than a level of performance indicated by the first die-specific performance grade indicator, preventing operation of the IC.

Abstract: Method and apparatus for inter-IC communication are described. In some examples, an integrated circuit (IC) includes core circuitry configured to process input data and provide output data; input/output (IO) circuitry configured to receive the input data, and transmit the output data; a control circuit configured to provide a selection signal; and an inter-IC communication port coupled between the core circuitry and the IO circuitry and configured to pass the input data and the output data, the inter-IC communication port having a memory interface and a memory controller, the inter-IC communication port configured to selectively couple either the memory interface or the memory controller between the core circuitry and the IO circuitry responsive to the selection signal.

Abstract: An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad.

Abstract: Some embodiments involve a circuit having first and second interfaces, and configurable structure to identify a selected integer number that is one of a plurality of different integer numbers associated with respective different configurations. In one embodiment, a conversion section organizes lines of the second interface into line groups equal in number to the selected integer number, and carries out a conversion operation in which it supplies to each line group a respective incoming data segment received through the first interface. In another embodiment, a conversion section organizes the lines of the first interface into line groups equal in number to the selected integer number, and carries out a conversion operation in which it supplies to the second interface a respective incoming data segment from each line group.

Abstract: A semiconductor device is provided that includes a substrate having opposing first and second surfaces and an interconnect structure extending between the first and second surfaces. A plurality of bond pads are located on the first surface of the substrate and the bond pads are electrically connected to the interconnect structure. The bond pads each have two or more micro-bumps, with the two or more micro-bumps on each bond pad being arranged to electrically connect the bond pad to one die pad of a semiconductor die. A plurality of external contacts are located on the second surface of the substrate and the external contacts are electrically connected to the interconnect structure.