Abstract: An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.

Abstract: An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger.

Abstract: Methods and devices for encoding and decoding video data are provided, wherein an image data structure can be represented as a group of macroblocks and each macroblock contains a plurality of blocks. One inventive aspect includes a method of decoding image data comprises decoding a current block of data, comprising retrieving a related reference block, decoding texture information of the current block, and reconstructing the current block, prior to the decoding of another block of data.

Abstract: Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a device handler for moving the packaged IC; a testing station for testing the packaged IC; and a pre-test conditioning station configured to remove at least a portion of an oxidation layer formed on contacts of the packaged IC prior to testing. In some embodiments, a method for testing packaged ICs may include providing a packaged IC to be tested; at least partially removing an oxidation layer from contacts of the packaged IC prior to testing; inserting the packaged IC into an interface structure; and testing the packaged IC.

Abstract: Method and device for arbitration for time division multiple access using delta-sigma modulation for an integrated circuit are described. A method for arbitrating access to a shared resource among multiple devices includes obtaining a first arbitration factor. The first arbitration factor is first delta-sigma modulated to produce a first slot signal. The first slot signal is for Time Division Multiple Access-arbitrated access to the shared resource.

Abstract: A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization. The test environment further can include a hardware verification language shell configured to randomly generate signals which indicate one of the instances and provide the signals to the test harness. The test harness selects one of the instances according to the signals.

Abstract: Approaches for reporting hardware events from circuitry implemented in an integrated circuit (IC). The IC is configured with a circuit to be analyzed and an event monitor circuit. A process invokes an application programming interface (API) function that references an operating system managed object. The API function includes a parameter value that references the object. The process is operated in a first manner when the object is in a first state. An interrupt signal is generated by the event monitor circuit to the processor in response to an input signal from the circuit under analysis, which initiates execution of an interrupt handler. The object is placed in a second state by the interrupt handler. The process is operated in a second manner different from the first manner in response to the object transitioning to the second state.

Abstract: A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.

Abstract: A method and apparatus for a pre-biasing storage mechanism to prevent oxidation and other contaminants from forming on the probe tips and probe tails of a probe card. The pre-biasing storage mechanism imposes a positive bias on the probe needles of the probe card so as to create physical contact between the probe tails and the conductive pads of the printed circuit board (PCB) arrangement of the probe card during a disengaged state of the probe card. In addition, the storage mechanism imposes a positive bias on the probe needles of the probe card, so as to create physical contact between the probe tips and a probe tip cleaning pad, or other protective surface, during a disengaged state of the probe card.

Abstract: A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.

Abstract: Disclosed is a contactor interconnect in an integrated circuit device test fixture comprises a plurality of contactor pins enabled to provide electrical contact with the contact points of an integrated circuit device, the contactor pins being mounted in the test fixture; and an electrical circuit coupled to two or more of the contactor pins of the test fixture, wherein the electrical circuit is isolated from other contactor pins of the plurality of contactor pins and wherein the electrical circuit is coupled to the two or more contactor pins by an electronically direct pathway.

Abstract: A method of compressing data can include forming at least one container by grouping calls of data according to at least one data element of each call. The method can include arranging, via the processor, calls of the at least one container into a plurality of segments according to a minimal coordinate set and extracting common coordinates corresponding to a first coordinate type from the plurality of segments. Coordinates of a second coordinate type of each segment of the at least one container can be replaced with a segment start coordinate and first distance information specifying the coordinates of the second coordinate type. The common coordinates of the at least one container can be replaced with a common start coordinate and second distance information.

Abstract: A top-level directory of a virtual file system is created. A hierarchy of directories is created under the top-level directory including creating a first file that contains an architecture description of the multi-device circuit arrangement. The directories have names indicative of the plurality of devices and configurable resources of the plurality of devices of the architecture description specified in the first file. A first set of one or more files is created that contain state data or configuration data for configuring resources of the plurality of devices to perform functions specified by the configuration data. A mapping of the configuration data to the resources of the plurality of devices is determined, and configuration data is stored in the configurable resources according to the mapping.

Abstract: A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.

Abstract: A circuit measures a time interval between a first event and a second event. One or more activity inputs receive a respective signal indicating the first and second events. For each activity input, a respective high-speed serial receiver includes a sampling circuit and a deserializer. The sampling circuit generates sample bits from sampling the respective signal at active edges of a clock signal. The deserializer converts the sample bits into a sequence of parallel data words. The sample bits undergo a first change in response to the first event and a second change in response to the second event. An arithmetic circuit receives the sequence of parallel data words from the respective high-speed serial receiver. The arithmetic circuit determines a number of the sample bits between the first and second changes in the sequence of parallel data words. The number measures the time interval between the first and second events.

Abstract: Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.

Abstract: A computer-implemented method of developing a packet processing application can include receiving a user input specifying a first function and a second function and automatically generating a high level programming language description of the packet processing application including a packet data storage unit (605, 610, 615). Packet units can be stored within the packet data storage unit at locations determined according to the first function and the second function. The high level programming language description also can be stored (630).

Abstract: An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.