Abstract: A method of operating an input/output interface is described. The method comprises eliminating a current path into an output pin of an input/output interface while the input/output interface receives an operational power signal during a first mode of operation; and enabling the current path into the output pin of the input/output interface to limit a voltage magnitude externally applied to the output pin of the input/output interface during a second mode of operation.

Abstract: Approaches for synchronizing memory accesses in a dataflow computing system. A compute operation in the dataflow computing system is commenced in response to availability in a dataflow memory of each operand that is required to perform the compute operation. Output data from a compute operation is stored in the dataflow memory at completion of the compute operation. Write and read operations are supported for accessing an external memory. Accesses to the external memory are synchronized by storing synchronization tokens in the data flow memory. Each synchronization token signals when an address in the external memory may be accessed.

Abstract: An offset cancellation circuit can include an amplifier having a negative input, a positive input, and a single-ended output, wherein the positive input is configured to receive a reference voltage. The circuit also can include a capacitor having a first terminal and a second terminal. The first terminal can be coupled to the negative input of the amplifier. The capacitor can be configured to sample the offset voltage of the amplifier. The second terminal of the capacitor can be selectively coupled to the output of the amplifier.

Abstract: A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described.

Abstract: In one embodiment, a method and apparatus for triggering and capturing digital circuit signals are disclosed. For example, a logic analyzer according to one embodiment includes at least one trigger combination block and a state machine deploy in a memory coupled to the trigger combination block, where the state machine includes an input coupled to an output of the trigger combination block and an output coupled to a capture memory in which one or more digital circuit signals are stored.

Abstract: Embodiments of a method, apparatus and circuit for voltage regulation are disclosed. One embodiment of a circuit includes a first field effect transistor (FET) having a gate, a drain and a source. A current source is connected to the drain of the FET. A second FET has a source connected to the source of the first FET by a node. The second FET also has a gate. A low-pass filter circuit has an input connected to the gate of the first FET and an output connected to the gate of the second FET.

Abstract: An embodiment of the invention pertains to an integrated circuit that includes at least one data processing circuit that is configured to generate error data. The integrated circuit further includes a nonvolatile memory, and also a controller circuit that is coupled to the at least one data processing circuit and the nonvolatile memory. The controller circuit is configured to detect the error data. The controller circuit automatically initiates a write operation to store the error data in the nonvolatile memory in response to detecting the error data.

Abstract: A method of implementing output ports of a programmable integrated circuit is disclosed. The method comprises coupling control signals to predetermined output ports of the integrated circuit; setting, by the control signals, initial output values of the predetermined output ports during programming of the programmable integrated circuit; and enabling normal operation of the predetermined output ports after the programming of the programmable integrated circuit. An integrated circuit having programmable output ports is also disclosed.

Abstract: An integrated circuit (“IC”) in which a debug signal is fed back within a core block is disclosed. The core block generates the debug signal. The core block includes a hardened routing that routes the debug signal within the core block. The IC also includes a programmable routing, coupled to the core block, to route the debug signal external to the core block. The hardened routing transmits the debug signal at a faster rate than the programmable routing. Further, the IC includes a selection device, coupled to the hardened routing and the programmable routing, to select one of: the hardened routed signal or the externally routed signal. In addition, the IC includes an external debug circuit, coupled to the programmable routing, to condition the externally routed signal.

Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Abstract: Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.

Abstract: A circuit manages input and output formats of the packets of a communication protocol. The circuit includes representation blocks and distribution and gather blocks coupled to the representation blocks. Each representation block is associated with a respective descriptor of the input and output formats. Each representation block processes a value of the respective descriptor. One or more of the representation blocks is adapted to modify the value of the respective descriptor. For each packet input in the input format, the distribution block distributes the value of each descriptor for the packet to the representation block associated with the descriptor. For each packet output in the output format, the gather block gathers the value of each descriptor for the packet from the representation block associated with the descriptor. The input format is changed to the output format in response to representation blocks modifying the value of the respective descriptor.

Abstract: A method of processing data within a controller for a network can include, while frame lock is not established, detecting a first preamble and a second preamble within a data stream of the network (1210, 1235). Biphase units between the first preamble and the second preamble can be counted (1215). Frame lock can be acquired on the data stream responsive to determining that the first preamble and the second preamble are separated by a number of biphase units corresponding to a frame (1235). A synchronization signal indicating that frame lock has been acquired can be output responsive to acquiring frame lock on the data stream (1240).

Abstract: Systems and methods detect a communication received at receiving antennas from transmitting antennas. Each transmitting antenna transmits a symbol in a constellation. A sphere detector performs a depth-first search until the depth-first search terminates in response to a terminate signal requesting the result from the sphere detector. The depth-first search evaluates respective distances of one or mode leaf nodes in response to the communication received at the receiving antennas. The depth-first search selects the result from these nodes in response to the respective distances. The result includes a selected leaf node that identifies a corresponding symbol in the constellation for each transmitting antenna, with this symbol detected as transmitted by the transmitting antenna.

Abstract: A hybrid probe card and methods are provided. A plurality of uniform sized probe pins are provided in a probe card for performing wafer probe testing. The probe card also includes at least one enlarged probe pin having a current carrying capacity that is at least 25% greater than the current carrying capacity of the uniform sized probe pins. The enlarged probe pins are provided, e.g., to prevent damage to the probe pins caused by large current flow. Methods for identifying the probe pin locations where the enlarged probe pins should be deployed are described.

Abstract: A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

Abstract: A method of analyzing integrated circuit (IC) product yield can include storing, within a memory of a system comprising a processor, parametric data from a manufacturing process of an IC and determining a measure of non-random variation for at least one parameter of the parametric data using a pattern detection technique. The processor can compare the measure of non-random variation to a randomness criteria and selectively output a notification indicating that variation in the parameter is non-random according to the comparison of the measure of non-random variation to the randomness criteria.

Abstract: Methods and systems generate a manufacturing test of a programmable integrated circuit and optionally test the programmable integrated circuit with the manufacturing test. A netlist is generated that represents a specific user design implemented in programmable resources of the programmable integrated circuit. The netlist represents user registers that are implemented in a portion of the logic registers of the programmable logic resources. A virtual scan chain is added to the netlist. Scan-test vectors are generated from the netlist using automatic test pattern generation (ATPG). The scan-test vectors serially scan the portion of the logic registers via the virtual scan chain. The scan-test vectors are converted into access-test vectors that access the portion of the logic registers via a configuration port of the programmable integrated circuit. The programmable integrated circuit is optionally tested for a manufacturing defect with the access-test vectors.

Abstract: A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.

Abstract: An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus M·T time slots; automatically determining a subset of the M·T time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.