Abstract: A method for configuring programmable logic in an IC to implement instances of a relocatable circuit includes, for each instance, assigning a respective portion of an address space of a processor to the instance, configuring a respective interface circuit for translating the transactions accessing the respective portion of the address space into a fixed address space of the relocatable circuit, and selecting a respective region within an array of programmable logic and interconnect resources of the IC. The processor accesses the address space with read and write transactions issued on an interface bus. The relocatable circuit is independent of the address space assigned to the instances. Each region is configurable to implement an instance. The programmable logic and interconnect resources are configured to implement the instances and to couple each instance to the interface bus of the processor via the respective interface circuit, using a single copy of configuration data for the relocatable circuit.

Abstract: Within a system comprising a processor and a memory, a method of creating evaluation hardware within an integrated circuit can include automatically inserting, by the processor, a disable circuit block into a circuit design. The method can also include automatically selecting a location within the circuit design to insert the disable circuit block, and/or inserting an unlock circuit block into the circuit design, wherein responsive to receiving an unlock code, the unlock circuit block overrides the disable circuit block. The method also can include storing, within the memory, the circuit design comprising the disable circuit block.

Abstract: A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.

Abstract: A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (Rsub) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of Rsub depends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.

Abstract: In one embodiment, a method is presented for formation of a through-silicon via in a silicon substrate. A via is etched in the silicon substrate. A first layer of oxide film is deposited on side walls of the via and on a first surface of the silicon substrate. At least a portion of the first layer of oxide film formed on the first surface of the silicon substrate is etched, and a second layer of oxide film is deposited on side walls of the via and. A conductor is deposited in the via.

Abstract: A method of testing software can include maintaining a cache within at least one of a plurality of farm machines of a testing farm. Each cache can include at least one version of test ingredients. The method can also include receiving, within at least one selected farm machine, a request to perform a test involving a test version of the test ingredients and comparing the test version of the test ingredients with versions of the test ingredients stored within the cache of the selected farm machine. The method can also include selectively updating a version of the test ingredients stored within the cache of the selected farm machine according to the comparison.

Abstract: A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock is disclosed. The circuit comprises a plurality of data recovery circuits, each data recovery circuit coupled to receive a corresponding data stream of the plurality of data streams and having a phase shifter generating a clock signal used to receive the data stream; and a channel deskew circuit coupled to receive the output of each data recovery circuit and the pixel clock. A method of receiving video data is also disclosed.

Abstract: Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from ?K to ?1 for K a block size, and the second range is from 0 to K?1.

Abstract: A method performed by a system comprising a processor and a memory can include performing a global placement of a circuit design for a target programmable integrated circuit (IC) and clustering the circuit design using a selected size of cluster regions according to control sets identified within the circuit design. The method further can include determining a legalized placement of the clustered circuit design by solving a minimum cost network flow problem for the selected size of the cluster regions and the target programmable IC and assigning components to sites of the target programmable IC according to the legalized placement. The circuit design specifying the legalized placement can be stored within the memory.

Abstract: Embodiments of an integrated circuit driver, a method for operating integrated circuit driver, and predrivers are described. In one embodiment of the integrated circuit driver, a bias control circuit provides a bias signal for a first mode and a second mode. The bias signal has a first voltage level associated with operation in the first mode and a second voltage level associated with operation in the second mode. An output driver circuit receives the bias signal. In the first mode, the output driver circuit operates as a supply referenced driver, and in the second mode, the output driver circuit operates as a ground referenced driver.

Abstract: Approaches for protecting design information are disclosed. In one approach, a request for an IP core from an integrated circuit device is received, and the request includes identification information. An identifier range is determined from the identification information. The identifier range includes a plurality of unique device identifiers identifying a plurality of integrated circuit devices that are allowed to receive the IP core. The identifier range is downloaded to the integrated circuit device, which evaluates whether or not a unique device identifier that is stored on the integrated circuit device is within the downloaded identifier range. The IP core is programmed into the integrated circuit in response to the unique device identifier that is stored on the integrated circuit device being within the downloaded identifier range.

Abstract: Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

Abstract: A system for monitoring a device under test implemented within an integrated circuit (IC) can include at least one probe that detects a designated type of data transaction, where in response to detecting the designated type of data transaction, each probe outputs a single data transaction detection signal. The system also can include a data collector coupled to each probe, where the data collector stores an indication of each data transaction detection signal that is output by each probe. The data collector can be configured so that no value of any probed signal is stored.

Abstract: A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node.

Abstract: An A/D converter including a folding stage and a plurality of conversion stages is described. The folding stage determines a sub-range in which an input analog voltage falls and adjusts the input analog voltage by a folding voltage offset corresponding to the determined sub-ranges to produce a residue voltage. Each following converter stage determines a voltage range in which the residue voltage falls. The converter stage multiplies the residue voltage by a factor of N to produce an intermediate voltage. The conversion stage selects a cyclic voltage offset corresponding to the sub-ranges in which the residue voltage falls and adjusts the intermediate voltage by the cyclic voltage offset to produce a new residue voltage.

Abstract: A method of placing a circuit design in logic blocks of an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the logic blocks of the integrated circuit; determining clock skew for a clock tree providing clock signals to a plurality of memory elements of the integrated circuit; evaluating timing requirements associated with the circuit design; and transforming the circuit design to a placement configuration, wherein the placement configuration places the circuit design in the logic blocks of the integrated circuit according to the timing requirements of the circuit design and the clock skew for the clock tree.

Abstract: A method and apparatus for circuit design synthesis are described. An edge flow cost function is implemented to obtain edge flow costs for nodes of a network. A subject graph of the network is then mapped using the edge flow costs.

Abstract: A method of tuning an input/output (I/O) interface of a circuit design for a selected programmable integrated circuit can include determining whether the I/O interface meets a timing requirement and when the I/O interface does not meet the timing requirement, automatically adjusting a first timing setting of the I/O interface of the circuit design. The method can include iteratively determining whether the I/O interface meets the timing requirement, and responsive to each iteration, adjusting the first timing setting. The circuit design, including the adjusted first timing setting, can be output.

Abstract: A method is provided whereby a placement-based cost function is utilized to minimize leakage and dynamic power that is consumed by clock networks implemented within integrated circuits (ICs) such as field programmable gate arrays (FPGAs). An initial placement of clock signal loads is analyzed to determine whether an alternative placement of clock signal loads results in the reduction of the usage of vertical clock spines, or equivalently, the optimization of the cost function. Several desirable characteristics are obtained through strategic clock signal load placement within the FPGA in accordance with the cost function. First, the number of clock regions spanned by a particular clock signal is minimized. Second, interconnect capacitance within the clock region is also minimized. By minimizing the total capacitance of a particular clock network implemented within a clock region, the leakage and dynamic power consumed by the clock network within the clock region is also minimized.

Abstract: A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.