Abstract: A circuit for generating a delayed output in an input/output port of a device adapted to implement circuits operating on a range of voltages is disclosed. The circuit comprises a first terminal of a delay stage of said input/output port coupled to receive a signal to be output by the circuit; a first pass gate coupled to the first terminal; a capacitor having a first terminal coupled to the output of the first pass gate and a second terminal coupled to ground; a second pass gate coupled to the first terminal of the capacitor; and a second terminal of said delay stage of said input/output port coupled to the second pass gate and outputting a delayed signal based upon the second pass gate. A method of generating a delayed output in an input/output stage of a device adapted to implement circuits operating on a range of voltages is also disclosed.

Abstract: A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.

Abstract: Methods of testing a user design implemented in a programmable integrated circuit (IC). The programmable IC is programmed with a first test design that includes the user design and a first test circuit, and a first test pattern is run. The programmable IC is then programmed with a second test design that includes the user design and a second test circuit, and a second test pattern is run. If one of the test patterns fails and the other passes, the programmable IC passes the test sequence. Because one of the test patterns passed, the error in the other test pattern must have occurred in the test circuit, which is not necessary for the functioning of the user design in the programmable IC. Thus, the success of one test pattern shows that the flawed resource is not included in the portion of the programmable IC utilized for implementing the user design.

Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M?1) and 2(M?1)?1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

Abstract: A method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to each component of the circuit design. The components of the circuit design can be clustered by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed to minimize critical connections. The circuit design can be declustered to perform additional placer optimization tasks on the declustered circuit design.

Abstract: A clock interface for a media access controller in a programmable logic device is described. The media access controller includes a clock generator for providing a clock signal to configured configurable routing of the programmable logic device to obtain a loaded version thereof. The loaded clock signal is provided to a clock network of the media access controller and to a delay cell of the media access controller to obtain an indication of the loading by the user instantiated design.

Abstract: A multi-stage phase detector (four stages in one described embodiment) comprises a plurality of data paths and phase paths that are buffered from a received serial data input stream to reduce loading. Each data path recovers a data bit and further functions as a transition detector to detect consecutive data bits having similar logic states. An exclusive NOR gate in the data path produces a control signal to disable a multiplexer in the phase path when two data bits have similar logic states. Each phase path produces a sample of a serial data input stream and produces the sample to a multiplexer for coupling to a transconductance module. The multiplexer output is coupled to or decoupled from the transconductance module by the control signal from the data path to maintain phase-lock.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

Abstract: A method and apparatus for the calibration of current cells, whereby a current signal from each current cell may be generated by either a thermometer current cell, or a binary current cell. If generated by a binary current cell, then two or more replica binary current cells exist to form a group of binary current cells within two or more binary current cell sets. The current magnitude generated by each replica current cell of each binary current cell group is first calibrated to be substantially equal to each other. Next, the combined current generated by the replica current cell group is calibrated to be substantially equal to a magnitude of a temporary current signal, or a portion thereof. Subsequent less-significant binary current cell groups are similarly calibrated to the temporary current signal through the use of the previously calibrated, more-significant binary current cell groups.

Abstract: A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base of the contact pad; a plurality of projections extending from and substantially perpendicular to the flat portion; and a solder ball attached to the projections and the flat portion. A method of forming a contact pad is also disclosed.

Abstract: A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a relationship between layers and device types of the integrated circuit device; and generating a layout-versus-schematic rules file using the implant table file.

Abstract: An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.

Abstract: A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the input signal based on a squared input signal and a squared reference signal.

Abstract: According to an example embodiment, a data-transfer circuit transfers high-speed input data toward an output port by coupling the data circuit selectively through a resistive-impedance circuit and a capacitive-impedance circuit to accommodate both high-frequency and low-frequency components of the input data signal. In a particular implementation, the control circuit can selectively control the data-passing circuit path by causing the input data to pass through the resistive-impedance circuit and therein pass low-frequency components of the input data signal while the capacitive-impedance circuit passes high-frequency components of the input data signal.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.

Abstract: The methods and circuits of the various embodiments of the present invention relate to deskewing a generated clock signal. According to one embodiment, a method of deskewing a clock signal in a circuit having a delay line comprises steps of measuring an intrinsic delay in a delay line; aligning the frequency of a generated clock signal with the frequency of a reference clock signal; and aligning the phase of the generated clock signal and the reference clock signal using the measured intrinsic delay. According to another embodiment, a circuit for deskewing a clock signal in a circuit having a delay line is also described.

Abstract: A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.

Abstract: A method of monitoring the functionality of a wafer probe is disclosed. The method comprises applying a multi-site probe to a plurality of semiconductor dies; comparing the failure rate of a first probe site of the multi-site probe with the failure rate of a second probe site of the multi-site probe for a test of the plurality of semiconductor dies; and determining that a probe site of the multi-site probe is defective based upon comparing the failure rate of the first probe site of the multi-site probe with the failure rate of the second probe site of the multi-site probe. A system for monitoring the functionality of a wafer probe site is disclosed.

Abstract: Method for in-system signal analysis is described. A programmable logic device is coupled within a signal communications system. A signal processing core is instantiated in programmable logic of the programmable logic device. At least one communication signal is provided to the programmable logic device, where the at least one communication signal has a first frequency. The at least one communication signal is sampled at a second frequency which is less than the first frequency to obtain samples thereof. The samples are converted from analog signals to digital signals. The digital signals are analyzed with at least in part the signal processing core.