Patents Assigned to Xilinx, Inc.
  • PMA RX in coarse loop for high speed sampling
    Patent number: 7493095
    Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: February 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Jerry Chuang, William C. Black, Scott A. Irwin
  • Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing
    Patent number: 7493543
    Abstract: Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 17, 2009
    Assignee: XILINX, Inc.
    Inventors: Vickie Wu, Arnold Louie
  • Double exposure semiconductor process for improved process margin
    Publication number: 20090042389
    Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Applicant: Xilinx, Inc.
    Inventor: Jonathan Jung-Ching Ho
  • Method and system to recreate instruction and data traces in an embedded processor
    Patent number: 7490227
    Abstract: A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Goran Bilski, Jorge Ernesto Carrillo, Usha Prabhu, Navaneethan Sundaramoorthy
  • Reset manager
    Patent number: 7490311
    Abstract: A reconfigurable module in a programmable logic device (“PLD”), such as a field-programmable gate array (“FPGA”), is reset after reconfiguration by an internal reset signal. The internal reset signal allows other modules in the PLD to remain active while the reconfigurable module is reconfigured and reset. The internal reset signal is generated by a reset manager circuit that optionally resides within the reconfigurable module.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventor: Benoit Payette
  • Power gating various number of resources based on utilization levels
    Patent number: 7490302
    Abstract: Power-gating circuit resources of an integrated circuit is described. The circuit resources are associated into sets responsive to utilization levels. The associating includes providing a first set of the sets, a first number of the circuit resources in the first set being associated with a first level of utilization. The associating also includes providing a second set of the sets, a second number of the circuit resources in the second set being associated with a second level of utilization. The first number is less than the second number responsive to the first level of utilization being greater than the second level of utilization. The circuit resources of the first set are commonly coupled to a reference voltage level via a first gating circuit. The circuit resources of the second set are commonly gated to the same or a different reference voltage level via a second gating circuit.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: February 10, 2009
    Assignee: XILINX, Inc.
    Inventors: Arifur Rahman, Sean W. Kao, Sathaki Das, Tim Tuan
  • Signal adjustment for duty cycle control
    Patent number: 7489173
    Abstract: Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated responsive to the first sample clock signal, where the first phase signal is out of phase with respect to the second phase signal. The second sample clock signal configured to be swept in phase in relation to the first phase signal. A combined signal is generated where the combined signal has a duty cycle associated with the first phase signal and the second phase signal in combination. A first counter and a second counter are clocked responsive to the second sample clock signal to count. A first count from the first counter is divided by a second count from the second counter to obtain the duty cycle associated with the combined signal.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Himanshu J. Verma, Kwansuhk Oh
  • Partition-based incremental implementation flow for use with a programmable logic device
    Patent number: 7490312
    Abstract: A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Emil S. Ochotta, William W. Stiehl, Eric Shiflet, W. Story Leavesley, III
  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Patent number: 7489152
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • High bandwidth reconfigurable on-chip network for reconfigurable systems
    Patent number: 7482836
    Abstract: A crossbar switch is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules, the crossbar switch providing communication links between the modules. The modules and crossbar switch can be easily updated in a partial reconfiguration process changing only portions of modules and the crossbar switch while other portions remain active. The crossbar switch uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: January 27, 2009
    Assignee: Xilinx, Inc.
    Inventors: Delon Levi, Tobias J. Becker
  • System for measuring propagation delays
    Patent number: 7482886
    Abstract: An oscillator circuit includes an enable circuit to generate an initialization signal and includes a ring oscillator responsive to the initialization signal and having a plurality of synchronous elements connected in a loop, wherein each synchronous element comprises a synchronous input terminal, a clock terminal, a first asynchronous input terminal, and an output terminal coupled to the clock terminal of a next synchronous element and coupled to the first asynchronous input terminal of a previous synchronous element. The enable circuit is independent of a delay path of the ring oscillator, and the ring oscillator generates a test clock signal having a period that does not include any signal delays associated with the enable circuit.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: January 27, 2009
    Assignee: XILINX, Inc.
    Inventor: Christopher H. Kingsley
  • Bitstream compression for a programmable device
    Patent number: 7482954
    Abstract: Method and apparatus for processing configuration data for a programmable logic device is described. The configuration data includes a sequence of frames. In one example, bits in the sequence of frames are identified as “don't care” bits that do not affect the functionality of a design implemented in the programmable logic device. Frames in the sequence of frames are compared to identify at least one set of identical frames, where the “don't care” bits are deemed to result in matches. Each of the at least one set of identical frames is merged to produce a respective at least one merged frame. Each of the at least one merged frame is associated with a plurality of configuration memory addresses in the programmable logic device. Each of the at least one merged frame may be loaded into configuration memory of the programmable logic device using a multi-frame write process.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: January 27, 2009
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Network media access controller embedded in a programmable logic device—host interface
    Patent number: 7484022
    Abstract: A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 27, 2009
    Assignee: Xilinx, Inc.
    Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
  • Analog front-end having built-in equalization and applications thereof
    Patent number: 7480347
    Abstract: An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: William C. Black, Charles W. Boecker, Eric D. Groen
  • Pull-up voltage circuit
    Patent number: 7480192
    Abstract: A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor and an n-type transistor are commonly gated to receive output from a first output node of the inverter to a first input node. A source region of the n-type transistor is coupled to a ground. A drain region of each of the first p-type transistor and the n-type transistor are commonly coupled at a second output node. A second p-type transistor has a gate coupled to the second output node. A drain region of the second p-type transistor, a source region of the first p-type transistor, and an input of the inverter are all coupled to a line. A source region of the second p-type transistor is coupled to the first supply voltage.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: January 20, 2009
    Assignee: XILINX, Inc.
    Inventor: Huy Son Nguyen
  • Virtual file system interface to configuration data of a PLD
    Patent number: 7480789
    Abstract: Methods and apparatus are described for providing access to data in a programmable logic device (PLD). A hierarchy of directories and files are maintained in a virtual file system, which is registered with an operating system. The directories and files are associated with resources of a PLD. In response to program calls to file system routines that reference files associated with resources of the PLD, the virtual file system is invoked, and the virtual file system accesses state information in resources of the PLD.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Adam P. Donlin, Patrick Lysaght, Brandon J. Blodget
  • Circuit for digital frequency synthesis in an integrated circuit
    Patent number: 7479814
    Abstract: A circuit for frequency synthesis in an integrated circuit is described. The circuit comprises an oscillator circuit having a counter-controlled delay line. A delay register is coupled to the counter-controlled delay line. The delay register stores a delay value for the counter-controlled delay line. Finally, a phase synchronizer circuit, coupled to the oscillator circuit, controls the starting and stopping of the oscillator circuit. According to alternate embodiments, a control circuit is coupled to the oscillator circuit for changing the frequency synthesizer from a low frequency mode to a high frequency mode.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Alireza S. Kaviani, Maheen A. Samad
  • Configuration access from a boundary-scannable device
    Patent number: 7480843
    Abstract: Provision of configuration access to a programmable device such as a programmable logic device (PLD) via a boundary-scannable devices. In one embodiment a configuration controller is arranged to transfer configuration data that specify configuration access for the PLD. A scan controller is coupled to the configuration controller and arranged to generate boundary-scan signals responsive to configuration data from the configuration controller. At least one boundary-scannable device has a plurality of boundary-scan pins coupled to the scan controller, and a PLD is coupled to the boundary-scannable device.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventor: Neil G. Jacobson
  • Programmable differential signaling system
    Patent number: 7479805
    Abstract: A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Shi-dong Zhou, Gubo Huang, Andy T. Nguyen, Ronald L. Cline
  • Method and apparatus for reducing the number of test designs for device testing
    Patent number: 7480842
    Abstract: The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Jay T. Young, Ian L. McEwen, Reto Stamm