Abstract: A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are operably coupled to latch even and odd bits of a digital stream of data based on a recovered clock to produce even and odd latched bits. The detection module is operably coupled to produce a phase representative pulse stream based on the even and odd latched bits. The clock recovery module is operably coupled to produce the recovered clock based on the phase representative pulse stream. The compensating module is operably coupled to adjust biasing of the even and odd latches based on operating parameter changes of the clock and data recovery circuit. The data recovery module is operably coupled to produce recovered data from the even and odd latched bits based on the recovered clock.

Abstract: The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. The system comprises a first integrated circuit having an output circuit for generating phase shift keying signals and a second integrated circuit having an input circuit for decoding the phase shift keying signals. The output circuit may include a ring oscillator for generating multiple clock signals that are phase-locked to one another.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: A packaged integrated circuit (“IC”) includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.

Abstract: A method of creating relatively placed macros (RPMS) for a circuit design for a target device can include determining N best configurations for each of a plurality of connections of the circuit design, wherein each configuration specifies relative positioning of a source and a load of a connection and an estimated delay for the connection. The method can include calculating a maximum allowable delay for each of the plurality of connections of the circuit design and determining that a connection selected from the plurality of connections is critical according to the N best configurations associated with the critical connection and the maximum delay of the critical connection. A configuration from the N best configurations associated with the critical connection can be selected. An RPM for the critical connection can be generated using the selected configuration.

Abstract: A method for estimating jitter of an integrated circuit design is described. A description of logic blocks of the integrated circuit design is obtained. A description of input/output blocks of the integrated circuit design is obtained. A first type of a first jitter induced by operation of a logic block onto one or more first clock signals external to the logic block is determined. A second type of a second jitter induced by operation of an input/output block on one or more second clock signals external to the input/output block is determined.

Abstract: Timing analysis of integrated circuits fabricated in different Fabs is described. A first speed file and a second speed file for a type of integrated circuit respectively fabricated in a first Fab and a second Fab are generated, the first speed file and the second speed file having corresponding types of delays. At least a portion of the corresponding types of delays have different delay values. A circuit design using the first speed file is compiled. The circuit design is for instantiation in programmable logic of the type of integrated circuit. The method further includes checking whether the circuit design as compiled using the first speed file passes timing constraints of the circuit design using the first speed file and checking whether the circuit design as compiled using the first speed file passes the timing constraints of the circuit design using the second speed file.

Abstract: Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.

Abstract: A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.

Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to configure peer system components. During configuration of the peer system components, other parameters used to configure those peer system components can also be propagated and used to configure other system components during customization of the FPGA-based SoC.

Abstract: A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of the FPGA, reducing overall design time and PROM storage space needed for the design. The design rules for the method include a requirement that the same frames oriented in the same relative location be available in dynamic areas where a bit stream will be located. Further, the rules require the same relative communication interfaces be available between the dynamic areas and static areas when the bit stream is relocated. Additionally the design rules require global resources, such as clock resources used by the static areas remain the same when the bit stream is relocated.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

Abstract: Methods and tools for detecting and correcting problems arising in the configuration process of a programmable logic device are described. An analyzer is used to aid a user in debugging the configuration process. The analyzer can access the programmable logic device through a boundary scan architecture such as JTAG. The analyzer can step through the configuration process, capturing the data received by the programmable logic device at each step, and compare that captured data with expected data. Mismatches can indicate errors in the configuration process, and the analyzer can help a user correct such errors.

Abstract: A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the randomly selected configuration of the testbench. During a subsequent processing pass, the method can include compiling the testbench in accordance with the configuration data. Simulation can be performed using the testbench.

Abstract: Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design block, with the first bus being an interface bus of a processor. An interface description is determined for a bus functional model of the interface bus of the processor. The interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench. A hardware specification is generated that couples the first bus of the design block with the interface description, and couples the HDL testbench with the second bus of the design block and with the synchronization bus of the interface description. The simulation for verifying the design block is automatically generated from the bus functional model and the hardware specification.

Abstract: Systems, methods, software, and techniques implementing a multiplexer mapper tool can be used to construct a binary decision diagram (BDD) or related structure representing a series of dependent multiplexers. Once in this form, the BDD can be manipulated in a variety of ways including reordering of nodes according to multiplexer selector and minimizing the BDD using conventional techniques. Once properly processed, the BDD can be further separated into smaller BDDs and mapped to existing cell library design elements.

Abstract: Generation a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a first partial remainder, which has a fixed width greater than or equal to the width of the second polynomial, from the first polynomial excepting a least significant portion. The first adder is adapted to generate a sum of the least significant portion of the first polynomial and a most significant portion of the first partial remainder. The second sub-circuit is adapted to generate a second partial remainder from the sum. The second adder is adapted to generate the remainder from the second partial remainder and the first partial remainder excepting the most significant portion.

Abstract: Computer-implemented methods of mapping a logical representation of a memory to physical memory, e.g., in a programmable logic device (PLD). The logical representation of the memory is input into the computer, which generates an initial solution (e.g., a column-based solution) for the memory. In a column-based solution, the primitives are arranged such that each column includes only one type of primitive. The column-based solution generated in this step uses the minimum number of primitives attainable by a column-based approach. The column-based solution is then modified to reduce multiplexing, e.g., by replacing two primitives that are cascaded in depth with two primitives that are cascaded in width. In some embodiments, the total number of primitives can be reduced by the modification. The resulting physical representation of the memory is then output, and can be utilized, if desired, to create an implementation of the memory targeted to a PLD.

Abstract: The multi-mode phase and data detector includes a phase detector and a charge pump. A plurality of latching blocks clocked on complimentary phases of a feedback signal produces a plurality of phase and transition signals. Based on a selectable bias level, latched comparators in the latching blocks operate to detect the multi-level input data signal as it crosses a plurality of threshold levels. Logic within the multi-mode phase and data detector selects subsets of exclusive OR gates from sets of exclusive OR gates and subsets of the latching comparators to place the multi-mode phase and data detector in one of a PAM-4, NRZ, or PRML mode of operation. The logic further selects subsets of latched comparators from the plurality of parallel coupled latches to further define the mode of operation of the multi-mode phase and data detector.

Abstract: An integrated circuit including a voltage generator for generating a body bias voltage is described. The voltage generator includes a charge source and a voltage regulator coupled to the charge source. Transistors are coupled to the charge source to receive the body bias voltage from the voltage generator.