Patents Assigned to Xilinx, Inc.
  • Method of forming silicide gate with interlayer
    Patent number: 7429526
    Abstract: A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: September 30, 2008
    Assignee: Xilinx, Inc.
    Inventors: Deepak Kumar Nayak, Yuhao Luo
  • Lid and method of employing a lid on an integrated circuit
    Patent number: 7429501
    Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 30, 2008
    Assignee: Xilinx, Inc.
    Inventors: Paul Ying-Fung Wu, Soon-Shin Chee, Steven H. C. Hsieh
  • Method of testing circuit blocks of a programmable logic device
    Patent number: 7430697
    Abstract: A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit; routing the test signal source to the logic circuit; and determining if the logic circuit is defective. According to an alternate embodiment, a method enables re-routing a path from a shift register to a lookup table to determine whether a lookup table is defective. According to a further alternate embodiment, a method enables localized routing to reduce the probability that a defect is a result of a routing defect.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: September 30, 2008
    Assignee: XILINX, Inc.
    Inventor: Deepak M. Pabari
  • Monitoring the state vector of a test access port
    Patent number: 7428674
    Abstract: Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: September 23, 2008
    Assignee: XILINX, Inc.
    Inventor: Neil G. Jacobson
  • Integrated system noise management—system level
    Patent number: 7428717
    Abstract: An integrated software tool for system noise management is described. A system noise management suite for an assembly includes an integrated circuit design to be coupled to a circuit board design. The system includes three modules and a user interface. The first module is configured to determine at least one type of bounce voltage for the assembly. The second module is configured to identify decoupling capacitances for the assembly to reduce power distribution system noise. The third module is configured to estimate jitter caused by the integrated circuit design. The user interface is coupled to the first module, the second module, and the third module for input of information for the first module, the second module, and the third module.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: September 23, 2008
    Assignee: Xilinx, Inc.
    Inventor: Anthony T. Duong
  • Enhanced incremental placement during physical synthesis
    Patent number: 7428718
    Abstract: A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: September 23, 2008
    Assignee: XILINX, Inc.
    Inventors: Amit Singh, Kamal Chaudhary
  • Error checking parity and syndrome of a block of data with relocated parity bits
    Patent number: 7426678
    Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: September 16, 2008
    Assignee: Xilinx, Inc.
    Inventors: Warren E. Cory, David P. Schultz, Steven P. Young
  • Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system
    Patent number: 7426709
    Abstract: An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bus should be used. In one embodiment, a latency constraint is used to determine whether a lower latency design with arbitration logic at the slave modules is to be used. In one embodiment, throughput constraints are used to determine whether a higher throughput design with arbitration logic at the slave modules is to be used.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: September 16, 2008
    Assignee: Xilinx, Inc.
    Inventor: Satish R. Ganesan
  • Method of adaptive equalization for high-speed NRZ and multi-level signal data communications
    Patent number: 7426235
    Abstract: Circuitry for equalizing a high data rate serial data stream that receives low frequency and high frequency test tones, accurately measures an amount of attenuation experienced by the high frequency test tone in relation to the low frequency test tone, and accordingly, produces equalization data that results in a corresponding amount of equalization or pre-emphasis being added to an outgoing signal. More specifically, however, the present invention includes both open loop and closed loop systems for equalizing or adding pre-emphasis to a signal with attenuation. In the open loop transceiver system, a presumption is made that an amount of attenuation in both the outgoing and ingoing directions are equal. In the closed loop transceiver system, a receiver determines an amount of equalization and produces the equalization data to a remote transceiver.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: September 16, 2008
    Assignee: Xilinx, Inc.
    Inventors: Stephen D. Anderson, David E. Tetzlaff, Michael J. Gaboury, Matthew L. Bibee
  • Method and circuit for decoding an address of an address space
    Patent number: 7426583
    Abstract: Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: September 16, 2008
    Assignee: XILINX, Inc.
    Inventors: Paulo L. Dutra, Jorge Ernesto Carrillo, Goran Bilski
  • Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM)
    Patent number: 7425843
    Abstract: Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: September 16, 2008
    Assignee: Xilinx, Inc.
    Inventors: Eric E. Edwards, Wayne E. Wennekamp
  • High speed transceiver receiving lower rate data
    Patent number: 7426252
    Abstract: A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module, an aligning module, a selecting module, and a memory module. The oversampling module is operably coupled to oversample an n-bit data word at an oversampling rate of m to produce an m by n bit oversampled data word, wherein the n-bit data word is received at a first data transmission rate that is less than a serial bit rate of the high speed transceiver. The transition boundary module is operably coupled to determine transition boundary data of the m by n bit oversampled data word in accordance with a clock of the high speed transceiver to produce transition boundary data. The selecting module is operably coupled to select representative bits in accordance with the transition boundary data to produce a recovered data word. The memory module is operably coupled to store the recovered data word.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 16, 2008
    Assignee: XILINX, Inc.
    Inventors: Jerry Chuang, Dai Huang
  • High speed transceiver operable to receive lower data rate transmissions
    Patent number: 7426251
    Abstract: A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module and a data recovery system. The oversampling module is operably coupled to oversample a unique alignment sequence and data of a data stream received at a first data transmission to produce an oversampled unique alignment sequence and oversampled data, respectively, wherein the first data transmission rate is less than a serial bit rate of the high speed transceiver.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: September 16, 2008
    Assignee: XILINX, Inc.
    Inventor: Dai Huang
  • Integrated circuit including a multiplexer circuit
    Patent number: 7423452
    Abstract: An integrated circuit including a multiplexer circuit and numerous memory cells are coupled to one another for improved performance. The multiplexer circuit includes a first input terminal and a second input terminal respectively coupled to an output of a first memory and an output of a second memory cell of the numerous memory cells. The multiplexer may also include select terminals coupled to a control signal and a complement of the control signal. An output of the multiplexer circuit is selectively coupled to one of four possible signals, where two of the four signals are the control signal and the complement of the control signal.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: September 9, 2008
    Assignee: Xilinx, Inc.
    Inventor: Manoj Chirania
  • Strain-silicon CMOS using etch-stop layer and method of manufacture
    Patent number: 7423283
    Abstract: Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 9, 2008
    Assignee: XILINX, Inc.
    Inventors: Yuhao Luo, Deepak Kumar Nayak
  • Method and apparatus for communicating data between a network transceiver and memory circuitry
    Patent number: 7424553
    Abstract: Method and apparatus for communicating data between a network transceiver and memory circuitry is described. In one example, a transmit peripheral includes a streaming interface configured to receive a communication sequence having data read from the memory circuitry. A receive peripheral includes a streaming interface configured to transmit a communication sequence having data to be written to the memory circuitry. Media access control (MAC) circuitry is configured to transmit the data read from the memory circuitry to the network transceiver, and receive the data to be written to the memory circuitry from the network transceiver.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: September 9, 2008
    Assignee: Xilinx, Inc.
    Inventors: Christopher J. Borrelli, Paul M. Hartke, Glenn A. Baxter
  • Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
    Patent number: 7424655
    Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: September 9, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Assigning inputs of look-up tables to improve a design implementation in a programmable logic device
    Patent number: 7424697
    Abstract: Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: September 9, 2008
    Assignee: XILINX, Inc.
    Inventors: Hasan Arslan, Anirban Rahut
  • Network media access controller embedded in a programmable logic device—address filter
    Patent number: 7421528
    Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: September 2, 2008
    Assignee: Xilinx, Inc.
    Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant
  • Programmable gate array and embedded circuitry initialization and processing
    Patent number: 7420392
    Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: September 2, 2008
    Assignee: XILINX, Inc.
    Inventors: David P. Schultz, Stephen M. Douglass, Steven P. Young, Nigel G. Herron, Mehul R. Vashi, Jane W. Sowards