Abstract: A lookup table (LUT) is programmable to function as a flip-flop. The LUT includes a plurality of memory cells, a plurality of transmission gates, and first and second logic gates. The transmission gates are coupled between the memory cells and an output terminal of the LUT to form a multiplexer circuit selecting one of a plurality of values stored in the memory cells and providing the selected value to the output terminal. First and second logic gates are included in two of the paths through the multiplexer, also providing first and second feedback paths within the LUT. These feedback paths enable the programmable implementation of first and second latches that form the flip-flop. Another subset of the memory cells can be optionally used to implement a function that drives the data input of the flip-flop.

Abstract: Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.

Abstract: A method and a system for transferring data between a register in a processor and a point-to-point communications link. More specifically, blocking and non-blocking methods are described to get and put data between a general purpose register of a soft or hard core processor and a queue connected to a point-to-point communications channel. One implementation example is for a Fast Simplex Link multi-processor network.

Abstract: A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (300 and 400) and is detected using differential receiver (600). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

Abstract: Apparatus and method for an address lookup table is described. The address lookup table for a packet includes: an Internet Protocol field, a router port field, a router port interface field, and a Media Access Control (MAC) address field. Where the Internet Protocol field, the router port field, the router port interface field and the MAC address field have a total bit length less than or equal to sixty-four bits.

Abstract: Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information are classified as input or output signals from an embedded core. Respective templates are automatically selected for the input signals and the output signals, respectively, at least in partial response to the wire lengths. Furthermore, timing information for the embedded core is obtained and classified according to condition, and the input signals and the output signals from the embedded core are determined to obtain rise and fall timing information for such signals.

Abstract: A circuit and method efficiently provide detection of corruption of data using an error correcting code (ECC). The circuit includes an ECC checker, a memory arrangement, and a detection circuit. The ECC checker generates a remainder of an ECC check of the data and an ECC value generated from an uncorrupted version of the data. The memory stores a set of values and receives a first portion of the remainder at a first address port and a second portion of the remainder at a second address port. The memory arrangement outputs a first value of the set responsive to a value of the first portion and output a second value of the set responsive to a value of the second portion. The detection circuit generates an error indication in response to the first and second values to indicate whether a single bit of the data is incorrect.

Abstract: Method and apparatus for digital calibration of an analog-to-digital converter (ADC). One example relates to calibrating an analog-to-digital (A/D) conversion system having an N-bit resolution. The A/D conversion system includes an ADC that generates an output having N most significant bits (MSBs) and M least significant bits (LSBs) (i.e., an N+M bit resolution). An offset calibration circuit is configured to determine an offset in the ADC and to compensate the N+M bit output using the offset to provide an N+M bit offset corrected output. A gain calibration circuit is configured to determine a gain correction factor for the ADC and to compensate the N+M bit offset corrected output using the gain correction factor to provide an N bit offset and gain corrected output.

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, may comprise a bus and a plurality of programmable masters configurable to interface the bus. A first portion of a memory may include configuration data operable to configure masters of the plurality, while a second portion of the memory may include access patterns to control when the different masters of the plurality may access the bus. An injection rate controller may control when a given master is to send data on the bus based on the access pattern associated with the master. A master controller may be operable to write the access patterns for the masters to the second portion of the configuration memory.

Abstract: An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA. The fingerprint is used as a key for an encryption system that protects against illegal use and/or copying of configuration data. In some embodiments, the propagation delay of various circuit elements formed on the FPGA are used to generate the fingerprint. In one embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In some embodiments, a ratio of measurable values may be used to generate the fingerprint. In other embodiments, differences in transistor threshold voltages are used to generate the fingerprint. In still other embodiments, variations in line widths are used to generate the fingerprint.

Abstract: Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.

Abstract: Method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

Abstract: A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.

Abstract: Methods of compensating for power supply variations in an integrated circuit. During operation of the IC die, a power supply voltage level is monitored. When the power supply voltage level drops below a specified level, a performance compensation circuit in the IC is enabled, bringing a first delay (e.g., the rising delay) for a compensated circuit in the IC more closely into alignment with a second delay (e.g., a falling delay) for the circuit. When the power supply voltage level exceeds the specified level, the performance compensation circuit is disabled. When the IC is a programmable IC, for example, the compensated circuit can be a programmable interconnect multiplexer of the programmable IC. In these embodiments, the power supply voltage level for the pass transistors in the interconnect multiplexer can be monitored and compensated for as described above.

Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Abstract: A system, device, and method for compensation of distortion caused by transmission line effects are disclosed herein. An output port including a feed-forward circuit parallel to the output impedance of an output driver compensates for distortion introduced by transmitting data over a transmission medium. The compensated output driver is utilized to transmit data between devices or circuits connected using conductive traces on printed circuit boards.

Abstract: Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

Abstract: A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Abstract: Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simulated on a hardware simulation platform. A first vector of data received by a co-simulation block is transferred to the simulated hardware-implemented block via a transfer function.

Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.