Abstract: Approaches for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit are disclosed. The electronic design includes at least one input/output bus associated with a plurality of the IOBs, and the IOBs for each input/output bus are assigned to respective sets. For each combination of pairs of the sets a respective weight factor is generated to indicate a degree of coupling between the first and second sets in the electronic design. An order of the sets is generated, and the sets are placed in an ordered series of input/output sites in the integrated circuit according to the order of the sets. A cost function is evaluated for the pairs of the sets. The generating of the order of the sets and the placing of the sets is conditionally repeated responsive to the evaluating of the cost function.

Abstract: Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (504). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced (506) for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced (510, 512) for then instance of the pre-implemented circuit design using the first physical implementation.

Abstract: Structures and methods that can be used to reduce power consumption in programmable logic devices (PLDs). Varying delays on the input paths of a PLD lookup table (LUT) can cause the nodes within the LUT (including the LUT output signal) to change state several times each time the input signals change state. Therefore, a programmable logic block for a PLD is provided that registers the LUT input signals instead of, or in addition to, the LUT output signal. The delays on the input paths are equalized and “glitching” on the LUT nodes is greatly reduced or eliminated. Thus, power consumption is reduced. Methods are also provided of reducing power consumption in PLDs by replacing single-bit registers on LUT output signals with multi-bit registers on LUT input signals, or by including multi-bit input registers in addition to the single-bit output registers.

Abstract: Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (310-1 through 310-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are circulated around the closed input/output loop. Operation of output blocks (210-1 through 210-N) is controlled responsive to a series of outputs (316-1 through 316-N) provided from a portion of the daisy-chain of registers (310-1 through 310-N) to selectively place an output block of output blocks (210-1 through 210-N) in an output mode responsive to the logic 1 output in the series of outputs while leaving the output blocks remaining in a non-output mode responsive to the logic 0s in the series of outputs. The output blocks (210-1 through 210-N) are commonly coupled at an output node (212) for coupling to a single test channel, as only one output block is in the output mode at a time.

Abstract: A digital high speed programmable delayed locked loop (DLL) includes a zero degree phase shift digital delay line, at least one intermediate phase shift digital delay line, a three hundred and sixty degree phase shift digital delay line, and a digital control module. The zero degree phase shift, intermediate phase shift, and 360 degree phase shift digital delay lines are operably coupled to produce, from a clock signal, zero phase shifted, intermediate phase shifted, and 360 phase shifted representations, respectively, of the clock signal. The digital control module is operably coupled to produce an intermediate control signal for the intermediate phase shift digital delay line and a 360 degree control signal for the 360 degree phase shift digital delay line based on a phase difference between the zero phase shifted representation of the clock signal and the three hundred and sixty degree phase shifted representation of the clock signal.

Abstract: An integrated circuit package having a lid is disclosed. The integrated circuit package comprises a substrate having an embedded conductor exposed on a surface; a lid comprising a plurality of conductive portions; and a solder bond between the embedded conductor and the plurality of conductive portions of the lid. The substrate may comprise a recess for receiving a flange associated with the walls. The embedded conductor preferably comprises a conductor coupled to a power or ground plane of the substrate. A standoff within the walls may optionally be soldered to a contact pad on the substrate. A method of assembling an integrated circuit package is also disclosed.

Abstract: Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i.e., PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e.g., utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e.g., rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.

Abstract: Decryption keys used in decrypting encrypted configuration data for a programmable logic device are erased following decryption of encrypted configuration data. A self-erasing key memory delivers a decryption key to a programmable logic device and then automatically erases itself. The keys are then no longer available outside the programmable logic device.

Abstract: Method and apparatus for true random number generation is described. One aspect of the invention relates to a digital logic circuit that includes N logic gates, where N is an integer greater than two. For each logic gate in the N logic gates: a first input terminal thereof is coupled to an output terminal thereof; a second input terminal thereof is coupled to an output terminal of a left neighbor thereof; and a third input terminal thereof is coupled to an output terminal of a right neighbor thereof. A sampling logic circuit may be provided to sample the output of the N logic gates to produce N-bit binary numbers. The N-bit binary numbers are true random numbers produced using pure digital logic without using an external source of randomness. A linear hybrid cellular automaton (LHCA) may be provided for scrambling output data of the sampling circuit.

Abstract: Circuits and methods of implementing flip-flops in dual-output lookup tables (LUTs). A flip-flop is implemented by programming a dual-output LUT to include a first function implementing a master latch and a second function implementing a slave latch. An output of the master latch is provided at a first output terminal of the LUT, and an output of the slave latch is provided at a second output terminal of the LUT. The output of the master latch (the first output of the LUT) is coupled to a first input terminal of the LUT, where it drives both the first and second functions. The output of the slave latch (the second output of the LUT) is coupled to a second input terminal of the LUT, where it drives the second function. A clock signal is provided to both first and second functions via a third input terminal of the LUT.

Abstract: Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU in a routing multiplexer included in each path simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.

Abstract: Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

Abstract: An extended bitstream, and generation thereof, for dynamically configuring a decoder. Content data is obtained to be encoded. Build settings are obtained for configuring the decoder. The content data is encoded with an encoder to provide encoded data. A configuration bitstream is generated for configuring programmable logic responsive to the build settings. The configuration bitstream is combined with the encoded data to provide the extended bitstream. The extended bitstream is self-contained to allow for configuring of the programmable logic to dynamically instantiate the decoder to decode the encoded data.

Abstract: A method is provided for building a simulation environment. A first functional model is produced that emulates the interaction of a processor with a first interface of a bus for the processor as controlled by a first script. A second functional model is produced that is controllable to emulate multiple interfaces. The second functional model is controlled to emulate a second interface of an input/output peripheral by a second script. A third functional model is produced that emulates a memory subsystem. A simulation environment is automatically generated that simulates the design block for a programmable logic device. The simulation environment couples the bus to the design block and the first and third functional models, couples the second interface to the design block and the second functional model, and couples the first and second functional models via a synchronization bus used for synchronizing between transactions of the first and second scripts.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: A design is used for coordinating channel bonding operations of a set of transceivers. The set include a master transceiver and a plurality of first level slave transceivers that perform channel bonding operations. Each first level transceiver is controlled by the master transceiver. The set also comprises a plurality of second level slave transceivers that perform channel bonding operations. Each second level transceiver is controlled by one of the plurality of first level transceivers. Any transceiver can be set as either a master, a first level slave or a second level slave. The design comprises a plurality of flip-flops and multiplexers, and is controlled by a MODE signal that determines the mode of operation of the design.

Abstract: A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.

Abstract: Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driver circuits coupled between the logic circuits. Each self-resetting interconnect driver circuit includes a multiplexer circuit driving a buffer circuit. In a first state, the buffer circuit drives a first value onto the output terminal of the buffer circuit. In a second state, the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state. Several different circuits are described in detail.

Abstract: Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.