Abstract: Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The programmable logic device supports secure and non-secure modes on a key-by-key basis, allowing users to write, verify, and erase individual keys without affecting others.

Abstract: A method of circuit design for a programmable logic device (PLD) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the PLD according to, at least in part, the reliability measures. The circuit design for the PLD can be routed using the selected routing resources.

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract: A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generates a large amount of heat when the circuit is clocked. The system monitors the temperature of the PLD and controls the switching of the circuit to achieve a predetermined temperature within a predetermined time period. The PLD is cooled, and the thermal cycling is repeated. The system detects microbump failures and communicates failure data to a computer for logging and analysis.

Abstract: Methods of compensating for process variations in an integrated circuit. Multiplexer circuits can be programmed to balance the rising and falling delays through the circuits in the presence of process variations. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of PLDs. During wafer sort or final test, a process corner can be determined for each die. One or more E-fuses can be set to predetermined level(s) to program the process corner information into the die, or the values can be stored in some other type of non-volatile memory. The stored values are utilized by the programmable multiplexer circuits to optionally adjust the rising and/or falling delays through the multiplexer circuits to achieve a balance between the rising and falling delays.

Abstract: According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.

Abstract: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.

Abstract: Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing continues by scrambling the input code word in accordance with the 1st scrambling protocol to produce a 1st scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1st scrambled code word based on the scrambling remainder. The process continues by combining the scrambled partial code word with the portion of the 1st scrambled code word to produce the transmit encoded output data.

Abstract: A dedicated Cyclic Redundancy Check (CRC) block within an Integrated circuit IC), for example, a Programmable Logic Device (PLD), allows direct access to the CRC block from within the programmable logic of the IC. Accessibility to the CRC block is achieved from any communication layer of the fabric due to the separation of the CRC block from the physical layer. All inputs and outputs of the CRC block are provided to the fabric to allow full controllability of CRC operation including data width, initial CRC value, and idle cycle introduction.

Abstract: A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the computer and the programming apparatus. A first component used to encode programming instructions and configuration data to form a first transmission stream that is transmitted to the programming apparatus in a single, long burst. The programming apparatus includes a second component of the software architecture that interprets the first transmission stream and programs the PLD using, for example, Boundary-Scan signals that are generated in response to the programming instructions and configuration data. A buffer memory stores data shifted out of the PLD during the programming operation, which is transmitted to the computer in a single, long burst after the first transmission stream is completed.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: A first hierarchical identifier is efficiently matched with a particular hierarchical identifier from a set of second hierarchical identifiers of a design in a high level modeling system. The matching tolerates name changes and additional design details in the hierarchical identifiers. A first sub-identifier at each level of the first hierarchical identifier is pattern matched with each second sub-identifier at a corresponding level of at least one second hierarchical identifier in a respective first subset of the second hierarchical identifiers. The pattern matching may include determining an edit distance between the first and second sub-identifiers. For each of the levels, a respective second subset of the respective first subset is determined in response to the pattern matching. The particular hierarchical identifier is selected from an intersection of all of the second subsets. The particular hierarchical identifier of the design is displayed on a user interface of the high-level modeling system.

Abstract: An interface between a programmable device and an external device coupled to the programmable device is described. The interface includes configurable control pins for providing control signals to the external device. The programmable device may be a field programmable gate array and the external device may be a nonvolatile memory. In some cases, the interface may be used to provide a byte-wide, or other parallel, interface. After configuration, the pins of the interface may be reclaimed and used for other purposes, such as accessing one or more external memories or other devices connected to a bus.

Abstract: An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output port, an object-sent port, an object-end port, a memory, and control logic. The data input port is coupled to the first processing element. The data output port is coupled to the second processing element. The object-sent port is configured to receive an object-sent signal from the first processing element. The object-end port is configured to send an object-end signal to the second processing element. The memory is configured to store objects, each of the objects include a plurality of data words. The control logic is configured to control reading and writing to the memory, processing the object sent signal, and generating the object end signal.

Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Abstract: Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a permanent basis, and methods of converting a PLD to an OTP device. In some embodiments, only the erase function is disabled in the device. Because programming data cannot then be erased from the device, the addition of new programming data is very unlikely to yield an operable design. Therefore, the programming function is also effectively disabled. The programming function can be directly disabled in addition to or instead of the erase function, if desired. The erase and/or programming functions can be disabled, for example, by blowing one or more fuses included in the erase and/or programming circuitry of the PLD.

Abstract: A test system configuration is provided to enable testing of integrated circuit (IC) packages. The test system includes a test controller, an interface apparatus including a PC board with lines connecting the test controller to contact areas for contacting the IC packages and a handler for supporting the IC chips and interface apparatus to maintain electrical connections during testing. The handler includes docking plates for attaching to the PC board to provide a guide for the IC packages that are inserted in openings of the docking plates to align contacts of the IC packages and PC board. The docking plates are configured to provide quad (four) and octal (eight) test sites, with either the quad or octal docking plate mating to the same PC board and being supported in the same handler system. An alignment frame for mounting either the quad or octal docking plate is further provided as part of the handler.

Abstract: Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler, a selector, the PLD, and a monitor. The generator selects sets of signals of the user design, and for each set of signals, generates a respective supplement of a subset of the user design supplementing the subset with a logic analyzer coupled to the set of signals. The compiler generates a respective configuration for each supplement. The selector selects a configuration or multiple configurations responsive to the specified set of signals and the sets of signals. The PLD implements the user design after the PLD is programmed with the selected configuration or configurations. The monitor accesses the specified set of signals in the PLD via the logic analyzer corresponding to each of the selected configuration or configurations.

Abstract: Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Abstract: A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.