Abstract: Method and apparatus for generating expected value data for testing a circuit configured in a programmable logic device (PLD). A simulation model is generated from a circuit representation for the circuit. Nodes in the simulation model configured for readback capture are automatically identified. The circuit representation is simulated as defined by the simulation model. Expected value data is recorded during the simulation in response to the identified nodes. A method and apparatus for testing a circuit configured in a PLD is also described. Expected value data for components of a circuit representation for the circuit is automatically generated using a modeling system, where the components are configured for readback capture. A test stimulus is applied to the circuit and state data is captured. The captured state data is compared with the expected value data.

Abstract: Crest factor reduction in a multiband transmitter is described. Component signals (xi[n]) are respectively obtained from constituent signals. The component signals (xi[n]) are respectively associated with sub-bands. A superposed signal associated with the component signals (xi[n]) is clipped to obtain a clipping noise error signal. The clipping noise error signal is applied to the component signals (xi[n]) using a least squares estimation to project clipping noise error onto the sub-bands.

Abstract: A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.

Abstract: Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Abstract: Adaptive transition density data triggered PLL (Phase Locked Loop). A novel solution is presented within a data triggered PLL whereby the missing data edge transitions may be detected and used to modify a phase difference between a data signal and a feedback signal and/or a current of a CP (Charge Pump) thereby maintaining a substantially constant loop bandwidth of the PLL for varying data edge transition rates. In one embodiment, an estimation of a substantially linear shift in PLL phase relative to the data phase is employed in the absence of data edge transitions. Alternatively, other means of implementing the shifts may be employed (e.g., non-linear) as desired in particular applications. This solution provides for a data triggered PLL that is practically impervious to variations in data edge transition density.

Abstract: Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering or generating a clock based with varying amounts of phase noise or jitter based upon a particular application. To achieve the foregoing, regulated and unregulated power are selectively provided to the circuitry for recovering a clock, to the circuitry for generating a transmission clock, and to any other circuitry having different tolerance levels for jitter and phase noise. Each power regulator comprises a current supply module and voltage regulator module. The current supply module provides one of a plurality of selectable output current levels into an output node of the regulator. The voltage regulator module having selectable voltage divider ratios at a first input of a comparator regulates an amount of current the device sinks from the output node to adjust the output voltage.

Abstract: An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that formats soft data received from an external storage device into a JTAG-compatible bitstream that can be used by the processor's test circuitry to access and/or control the processor's resources at any time, thereby allowing the embedded processor's resources to be accessed and controlled during FPGA configuration operations before the processor has been initialized to an operational state without using an external configuration tool. For some embodiments, the formatting circuit is a state machine that formats soft data such as firmware code, software programs, processor commands, and the like received from the external storage device into a JTAG-compatible bitstream that can be loaded into and/or used to access the resources of the embedded processor via the processors' test circuitry.

Abstract: The present invention relates generally to integrated circuit trays, and in particular, to an integrated circuit tray enabling communication with integrated circuit stored therein. A storage tray for storing integrated circuits according to one embodiment of the invention comprises a plurality of recesses adapted to receive an integrated circuit. A conductor extends between the plurality of recesses and comprises a plurality of contacts associated with the recesses. A terminal portion, such as a connector, is coupled to the conductor to enable programming the integrated circuits stored in the tray. Embodiments having additional components are also described. Further, embodiments for connecting a plurality of trays and enabling programming of integrated circuits in the plurality of trays are also described. A system for programming integrated circuits in a storage device is also described. Methods of communicating with a plurality of integrated circuits in a storage tray are also disclosed.

Abstract: An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into the shift register in synchronization with the output clock; input data is not loaded into the shift register on each cycle of the output clock, however, because the input clock is slower than the output clock. A clock comparison circuit compares the input and output clocks and tracks the history of data transfers into the shift register to determine whether a given input datum should be loaded into the shift register during a given period of the output clock. The clock comparison circuit writes input datum into the shift register periodically, skipping write cycles as necessary so that input and output data rates match.

Abstract: An integrated circuit has an optical waveguide configured to carry a plurality of optical channels, which in a particular embodiment are optical clock signals generated by an optical clock generator. The integrated circuit includes an optical crossbar having a first output, a second output, a first optical ring resonator, and a second optical ring resonator. In a further embodiment, the optical crossbar is an optical crossbar switch and an output path in the optical crossbar switch includes another tunable optical ring resonator and an intermediate waveguide, which allows isolating the output from any optical channel on the on-chip optical waveguide by tuning the first ring resonator to a first wavelength, and tuning the other ring resonator to another wavelength.

Abstract: A computer-readable medium is encoded with a computer program for directing a computer to convert a first bitstream operable to configure, for example, an earlier-generation PLD to a second bitstream operable to configure, for example, a later-generation PLD, wherein functionality is preserved from one PLD to another. The computer divides each PLD into similar regions, and replicates a function of each region of the first PLD in a corresponding region of the second PLD. The computer interconnects the regions of the second PLD to replicate the interconnections of the regions of the first PLD. The computer allows a user to manipulate the connection scheme of the second PLD.

Abstract: A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.

Abstract: A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through cells of the schematic data to generate a hierarchy of cells associated with a boundary scan chain. Each ignore cell in the hierarchy is pruned. Each short cell in the hierarchy is replaced with a direct connection. A shadow net is added to each net of the hierarchy. Each of the cells in the hierarchy is flattened in a bottom-up fashion.

Abstract: A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to sample the logic value of a test signal after the test signal has traversed a path under test (PUT). A counter is used to determine the number of logic high valued samples and the number of logic low valued samples during a test period. A ratio is then taken to determine the resulting duty cycle for the test period.

Abstract: A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).

Abstract: A voltage supply circuit for generating a composite bandgap reference voltage includes a single bandgap reference voltage circuit and a select circuit. The bandgap reference circuit has a first output to generate a first bandgap voltage having a first temperature coefficient and has a second output to generate a second bandgap voltage having a second temperature coefficient that is different from the first temperature coefficient. The select circuit has a first input to receive the first bandgap voltage, a second input to receive the second bandgap voltage, and an output to selectively provide either the first bandgap voltage or the second bandgap voltage as the composite bandgap reference voltage.