Abstract: A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.

Abstract: Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

Abstract: A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated control signal. When the control signal is de-activated, the latch is de-coupled from the first voltage supply terminal and coupled to the non-volatile memory cell. If the non-volatile memory cell is programmed, the latch is coupled to a second voltage supply terminal, thereby storing a second logic value in the latch. If the non-volatile memory cell is erased, the latch is isolated from the second voltage supply terminal, and the first logic value remains stored in the latch. The latch can also be directly written through one or more access transistors, thereby facilitating testing.

Abstract: Method and apparatus for implementing a circuit design for at least one integrated circuit on a circuit board is described. In one example, a logical description of the circuit design is obtained. For example, a functional description of the circuit design may be synthesized to produce the logical description. Logical pins in the logical description are assigned to input/output (I/O) elements of the at least one integrated circuit, and the logical description is placed and routed for the at least one integrated circuit, based on external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit.

Abstract: A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers, input multiplexers). Some interconnect lines can be used to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other programmable interconnect lines (e.g., straight interconnect lines and/or other diagonal interconnect lines) in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row).

Abstract: Low current differential signal/swing I/O interfaces and techniques can be implemented. An output interface converts input data signals to differential current signals for transmission over transmission lines. When the differential current signals are received by an input interface, they are converted to differential voltage signals and appropriately amplified.

Abstract: Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system (200) includes a set of n processing elements (202) for processing messages, where n is an integer greater than zero. A set of m memories (204) is provided for storing the messages, where m is an integer greater than zero. Multiplexing logic (206) is provided for coupling each of the processing elements to each of the memories. Control logic (208) is provided for driving the multiplexing logic to provide access to each of the memories among the processing elements in accordance with a gated module-n schedule.

Abstract: A method and structure for configuring a programmable logic device (PLD) from a serial peripheral interface (SPI) based serial memory. The type of the SPI memory is initially identified by the PLD. The PLD then selects the appropriate read command in response to the SPI memory type. The PLD then issues the read command to the SPI memory. In response, the SPI memory continuously provides a set of configuration data to the PLD. The PLD is configured in response to the configuration data. The PLD can identify the SPI memory type in response to control signals on pins of the PLD. Alternately, the PLD can identify the SPI memory type by performing a search. The search can include issuing a plurality of known read commands to the SPI memory, and then determining which read command causes the SPI memory to respond.

Abstract: A method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator are disclosed. A model of a phase locked loop to be simulated in a digital simulator includes a behavioral model for simulating a phase locked loop as a set of behavioral blocks based upon a high level description language and a loop filter model, used by the behavioral model, the loop filter model being implemented as a series of integrators based on a transfer function for creating a loop voltage for generating phase adjustments. The PLL behavior is based on actual circuit parameters and produces accurate behavior in a fraction of the time required using an analog simulator.

Abstract: Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.

Abstract: A receiver termination network is included in a high-speed receiver that also includes a receiver analog front-end and a data recovery module. The receiver termination network includes a DC matched termination circuit and an AC coupled bias circuit. The DC matched termination circuit is operably coupled to provide a termination of a transmission line coupling the high-speed receiver to a transmission source and to receive high-speed data via the transmission line. The AC coupled bias circuit is operably coupled to provide a common mode reference and to high-pass filter the high-speed data to produce filtered high-speed data. The receiver analog front-end is biased in accordance with the common mode reference and is operably coupled to amplify the filtered high-speed data to produce amplified high-speed data.

Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide-a count signal associated with external device latency. The count signal is captured responsive to the clock signal.

Abstract: The embodiments of the present invention relate to an improved printed circuit board having additional rows of ground vias to reduce crosstalk in the board. A printed circuit board according to one embodiment of the present invention comprises a first row of vias and a second row of vias, each having a plurality of signal vias. The circuit board also comprises a plurality of rows of vias being coupled to a ground plane between the first row of signal vias and the second row of signal vias. According to one embodiment, the plurality of rows of vias being coupled to a ground plane comprise rows of vias having different sizes. Some of the vias are designed to receive a component, while others are generally smaller and designed to provide a return current path for the signal vias.

Abstract: A data generator configured to provide a predictable data pattern, including system and product-by-process therefore, is described. The data generator is coupled to a circuit under test via a first data interface. The data generator is configured to generate a predictable data pattern for the circuit under test. The predictable data pattern is associated with display on a screen. A display controller is coupled to the circuit under test via a second data interface. At least one of a data monitor and a display device is coupled to the display controller.

Abstract: A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers driving the interconnect lines, input multiplexers driving the logic blocks). The interconnect lines can be used, for example, to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other diagonal interconnect lines in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row).

Abstract: A method is disclosed for redeploying an FPGA that has been restricted for use with a first design. The FPGA accepts only those configuration bitstreams whose CRC checksums match a value stored on the FPGA. The restricted FPGA is used with a second configuration bitstream for a second design by altering the second configuration bitstream so that it generates a CRC checksum that matches the value stored on the FPGA. The first checksum is derived by applying a CRC hash function to the first configuration bitstream. The second configuration bitstream is altered so that the second checksum generated when the CRC hash function is applied to the altered second configuration bitstream is identical to the first checksum. Altering the second configuration bitstream can result in an altered second configuration bitstream that is either longer than or the same length as the second configuration bitstream.

Abstract: Apparatus, method and system network for lead processing are described. More particularly, a web-based client-server system is described where a sales force automation system is used for updating databases and routing tasks based on user activity. In particular, action item form screen images and lead form screen images may be cast as objects and associated with one another. A lead source is identified with a lead, and activity with respect to whether such a lead results in a registration or a quote is tracked. Moreover, whether such registration or quote results in actual revenue generation is tracked as based on an existing opportunity or a new opportunity. Accordingly, lead source effectiveness for generating new business may be determined based on revenue generation.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: A dedicated protocol generation unit provides the ability to detect validity of data received from a configurable logic block, such as a programmable logic device (PLD). Data valid signaling is provided by the configurable logic block, such that invalid data received from the configurable logic block is replaced with programmable insertion data prior to transmission, while valid data is allowed to be transmitted without replacement. Also, data received by Input/Output (I/O) portions of the dedicated protocol generation unit are compared to programmable data patterns. After a positive comparison, matching data is either truncated and not delivered to the configurable logic block, or the matching data is delivered to the configurable logic block with appropriate data valid signaling.

Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.