Abstract: A programmably configurable logic-based macro is described. Portions of configuration logic blocks for interconnectivity are assigned. The portions are configured as respective shift registers. Interconnects are routed between design static locations associated to provide interconnectivity between the portions. The portions assigned and routed are saved as a macro file. Inputs and outputs of the macro file are defined in a hardware description language. The hardware description language definition of the inputs and the outputs of the macro file are synthesized to provide a bitstream for programming programmably configurable logic associated with the portions. A shift register-to-shift register module interface boundary is created within an array of the programmably configurable logic.

Abstract: A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an integer divide by N block. Based on a desired divider ratio, the state machine selects the new clock that is phase shifted with respect to a presently selected clock. Each change from the presently selected clock to the new clock produces a selected clock cycle that is expanded or contracted by the amount of phase shift between the new clock and the presently selected clock. The integer divide by N block divides the selected clock by the integer portion of the desired divider ratio producing a divided clock that is effectively divided by a non-integer amount.

Abstract: Method and apparatus for encoding image data is described. In an example, a memory stores bit-planes associated with the image data. Each of the bit-planes is partitioned into data units. A bit modeler communicates with the memory and produces modeled data in response to each of the data units for each of the bit-planes. An arithmetic coder communicates with the bit modeler and produces a coded data in response to each of the modeled data produced by the bit-modeler. In another example, the bit-modeler processes at least two of the bit-planes in parallel.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.

Abstract: A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.

Abstract: A method (10) of reducing a size of a netlist for a target architecture can include the steps of creating (12) a netlist of objects for the target architecture, identifying (14) objects specific to the target architecture that are repeated regularly to identify potential dummy objects, creating (15) a list of objects used by a design in the target architecture, and forming (16) a list of unused objects in the target architecture from the netlist of objects and the list of objects used by the design. The method can further include the steps of replacing (18) at least one object in the list of unused objects with an appropriate dummy object to form a modified netlist and simulating (19) the modified netlist.

Abstract: The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources and ensure the correct initialization of the CSoC. The CSoC leverages an on-chip central processing unit (CPU) to control the configuration process of the configurable system logic (CSL). Advantageously, the CSL configuration memory cells as well as other programmable locations in the CSoC are addressable as part of a system bus address space. The system bus is a multi-use structure that can be used for both configuring and reading of memory cells. In this manner, the CSoC optimizes system resources.

Abstract: An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

Abstract: Method and apparatus for decoding configuration data is described. A programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the programmable logic device via the configuration interface. The boot cores include a configuration decoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration decoder core provides a peripheral interface internal to the programmable logic device, and the boot memory contains at least one set of instructions for decoding encoded data and at least one library for writing decoded encoded data to configuration memory of the programmable logic device. The encoded data is obtained from data memory via the peripheral interface.

Abstract: A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.

Abstract: The generation of a netlist for an electronic system includes identifying one or more relocation blocks in a first system design hierarchy for the electronic system and determining a corresponding target block in the first system design hierarchy for each relocation block. The generation of the netlist further includes producing a second system design hierarchy from the first system design hierarchy by relocating each relocation block to the corresponding target block while maintaining connectivity for the one or more ports for each relocation block. The netlist is generated from the second system design hierarchy.

Abstract: A bandgap reference voltage circuit includes a bandgap circuit, a start-up circuit, and a recovery circuit. Upon device power-on, the start-up circuit provides a start-up current to initialize the bandgap circuit to a valid state, during which the bandgap circuit generates a substantially constant bandgap reference voltage. Once the bandgap circuit is in the valid state, the start-up circuit turns itself off. If the bandgap reference voltage falls to a level that causes the bandgap circuit to enter an invalid state, the recovery circuit turns on and provides a recovery current to the bandgap circuit that returns the bandgap circuit to the valid state, after which the recovery circuit turns itself off.

Abstract: A pre-driver for large I/O pull-up and pull-down transistors is provided so that the I/O pull-up and pull-down transistors do not experience crowbar current, and the pre-driver circuit likewise does not experience crowbar current or require large driver transistors. One pre-driver circuit includes two NAND gates and two NOR gates with delay circuitry provided by two series inverters from a data input to a first node, and two additional series inverters from the first node to a second node. A further pre-driver circuit includes feedback from the pre-driver outputs to ensure its NMOS and PMOS transistors do not turn on together to create crowbar, while allowing faster switching. With the pre-driver circuit embodiments, a conventional level shifter can be used. Further with the pre-driver circuitry, slew rate control can be provided in the pull-up and pull-down driver circuitry, rather than in the pre-driver circuitry.

Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.

Abstract: A programmable logic device having groups of data and instruction memory blocks separated by a processor block is described. The processor block including an embedded processor and data and instruction memory controllers. The data and instruction memory blocks respectively including data and memory groupings of block random access memories.

Abstract: A method of creating a circuit from a high level programming language (HLL) program can include generating a netlist from the HLL program, wherein the netlist specifies the circuit design (1320, 1325). The circuit design can be run within a programmable logic device and a plurality of execution threads can be identified at runtime to determine scheduling information (1335, 1340).

Abstract: Methods of reducing the amount of logic in a digital circuit without affecting the functionality of the circuit. A circuit description and one or more test patterns are supplied to a fault simulator. The fault simulator runs the test patterns on the circuit, and identifies any nodes that did not transition in either direction (“non-transitioning nodes”). If the test patterns provide full coverage of the desired functionality for the circuit, each of the non-transitioning nodes is unnecessary to the logical functionality of the circuit in the target application. Therefore, the logic driving the non-transitioning nodes is removed from the circuit. The modified circuit can then be re-simulated, if desired, to verify that the relevant functionality of the circuit has not changed.

Abstract: A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.

Abstract: A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

Abstract: A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.