Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: A method and test configuration for performing a gross I/O functionality test at wafer sort is described. The method uses a current injector, such as a pullup or a pulldown on an I/O pad, to inject current at the I/O pad, and based on the resulting voltage, determines if the I/O characteristics of the IC meet the performance criteria set by a manufacturer. In some embodiments, the test configuration can comprise an output buffer, which can be a tristate buffer, and/or an input buffer for verifying the performance of those components. The method and test configuration allow such tests to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.

Abstract: Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality of bus interfaces. Arbitration logic is configured for communication with the plurality of ports. The arbitration logic arbitrates access to the memory circuitry among the plurality of bus interfaces on a time shared basis.

Abstract: A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e.g., power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.

Abstract: Disclosed is a DC thermal energy generator for heating localized regions of an integrated circuit. The integrated circuit includes a pair of static circuits whose outputs are shorted, and are in contention. Contention causes current to flow through the circuits, generating heat. Integrated-circuit temperature can be varied by turning on more or fewer thermal energy generators. The thermal resistance of a packaged integrated circuit is computed using a well-known relationship among the integrated circuit's measured temperature, power consumption, and the ambient temperature.

Abstract: Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.

Abstract: Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.

Abstract: A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.

Abstract: A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

Abstract: A method and apparatus for transceiving data in a micro-area network includes processing that begins by obtaining a data unit for transmission by a first data transceiving entity of a micro area network. The processing then continues when the first data transceiving entity formats the payload data using a first transmission format convention. The first data transceiving entity also formats the overhead data using a second transmission formatting convention to produce formatted overhead data. The formatting of the overhead data and/or payload data may include encoding and/or modulating the data. The processing continues when the first data transceiving entity transmits the formatted payload data and the formatted overhead data to at least one target entity within the micro-area network. The process continues when a target entity receives the formatted payload data and the formatted overhead data.

Abstract: Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A virtual-to-physical address translator is configured to translate a virtual address to provide physical addresses and select signals, where the physical addresses are locations of at least a portion of data words of a cell stored in the concatenated memories in successive order. The multiplexers are coupled to receive the select signals as control select signaling to align the at least one data word obtained from each of the concatenated memories for lane aligned output from the aligner.

Abstract: A configurable latch is implemented using a configurable pulse generator and a level sensitive (LS) latch. The configurable pulse generator produces either a pulse signal that is aligned with the input clock edge, or simply provides the input clock signal to its output in response to a pulse generator control signal. If a pulse signal is provided to the latch, then edge triggered (ET) latch operation is effected within the latch. If, on the other hand, a clock signal is provided to the latch, then LS latch operation is effected within the latch. Thus, configuration of latch operation is established in response to the type of clock signal that is provided to the latch.

Abstract: A programmable integrated circuit (IC) provides high routing flexibility without the use of an output multiplexer structure. According to one embodiment, an IC includes programmable tiles arrayed in rows and columns. Output multiplexer structures are not included in the programmable tiles. Routing flexibility is provided in each tile by input multiplexers coupled between a general interconnect structure and the input terminals of a logic block, and by providing direct access from the logic block output terminals (e.g., lookup table outputs and memory element outputs) to both horizontal and vertical interconnect lines. In some embodiments, the logic block output signals can also drive “diagonal” interconnect lines in the general interconnect structure.

Abstract: An integrated circuit (IC) includes volatile memories, at least one non-volatile memory, at least one control circuit, and a configurable logic array. Each volatile memory has an associated interface including a respective first input and a respective second input. The control circuit is coupled to the volatile memories and the non-volatile memory. The control circuit stores respective contents from each volatile memory in the non-volatile memory responsive to the respective first input, and loads the respective contents into each volatile memory from the non-volatile memory responsive to the respective second input. The configurable logic array is coupled to the volatile memories and is configurable to control each first input and each second input.

Abstract: A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.

Abstract: Methods of programming an integrated circuit (IC) such as a programmable logic device to avoid localized defects present in the IC, and ICs capable of performing these methods. As part of an automated programming process, programmable resources utilized by a user design are tested, and the implemented user design is modified to avoid any defective programmable resources that are detected. The modifications can include, for example, rerouting one or more internal signals and/or substituting a fully functional programmable resource for a defective programmable resource. These methods are carried out by testing and implementation logic included in the IC. Design information such as a software device model, test program, test data, place and route program, and/or resource swapping program can be optionally included in the configuration logic or supplied in an expanded bitstream applied to the inventive IC. In some embodiments, the modified bitstream is written to an external memory device.

Abstract: A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks (are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation unit is configured to provide a lock signal and sequence information to the section controllers in each of the pipeline blocks. The section controllers are configured to maintain in order inter-pipeline execution of the sequence responsive to the sequence information and the lock signal.

Abstract: Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.