Abstract: Creating virtual extender plugins using MGTs (Multi-Gigabit Transceivers). A virtual extender plugin allows a user seamlessly to bridge between various FPGAs (Filed Programmable Logic Arrays) when designing and implementing electronic devices. These bridges, provided by these virtual extender plugins, allow for efficient use of various untapped resources within a device. For example, a given FPGA may employ virtual extender plugin(s) to access and use various untapped (or relatively lightly tapped) functionality of other FPGAs. These virtual extender plugins may be implemented according to a relatively wide variety of applications allowing the tapping of unused resources such as memory, microprocessor peripherals, LUTs (Look Up Tables), IOs (Input/Output devices and/or ports), memory, and embedded microprocessor blocks.

Abstract: Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

Abstract: A semiconductor device has an NMOS portion and a PMOS portion. A first stress layer overlies a first channel to provide a first stress type to the channel and a first modified stress layer is formed from a portion of the first stress layer overlying a second channel. A second stress layer providing a second stress type overlies the first modified stress layer and a second modified stress layer is formed from a portion of the second stress layer overlying the first stress layer.

Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to configure peer system components. During configuration of the peer system components, other parameters used to configure those peer system components can also be propagated and used to configure other system components during customization of the FPGA-based SoC.

Abstract: A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.

Abstract: A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL1) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN1) and a PMOS transistor (MP1) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN1) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP1) compensates for voltage undershoot conditions at the pad.

Abstract: Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to memory cells that drive the gates of the transistors, memory cells that drive the sources of the transistors, and level shifters that drive the gates of the transistors. In these techniques, an appropriate gate to source voltage (VGS) can be applied to a transistor in its off state. Of importance, this VGS can under-drive the transistor, which significantly reduces the sub-threshold leakage of that transistor. These techniques fail to affect a transistor in its on state, thereby ensuring that high speed performance of the integrated circuit can be maintained.

Abstract: Translation of an electronic design of an integrated circuit into circuit description language is described. In an example, a connection among circuit descriptions representing behavior of circuit elements in the electronic design is identified. The connection is associated with an identifier. The electronic design is then translated into a circuit description language representation, where the connection is implemented within the circuit description language representation using the identifier. In another example, an implicit circuit description representing behavior of circuit elements within the electronic design are identified. Explicit circuit descriptions within the electronic design are augmented with an addition circuit description. The electronic design is then translated into a circuit description language representation.

Abstract: Efficient implementations of wide logic functions (e.g., priority encoders, AND gates, OR gates) in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate first and second function output signals. The first and second functions can optionally share some or all of the input signals. The first function output signal drives the select terminal of a carry multiplexer, which selects between a carry in input signal and the second function output signal to provide the carry out output signal. The wide function result is provided by the final carry multiplexer in a chain of such carry multiplexers. In an exemplary wide AND gate, the first function is an AND function, and the second function is ground. In an exemplary wide OR gate, the first function is a NOR function, and the second function is power high VDD.

Abstract: The present invention relates to a graphical user interface for a system that compiles MATLAB models for synthesis into register transfer level code. The graphical user interface provides a visual representation of the design in a manner that allows the user to more easily understand the algorithm being modeled. From this interface, the user may also modify the type, size and dimensions of variables from dialog boxes. The system allows the user to efficiently compare and verify a fixed-point design versus the MATLAB design. The interface allows the user to then make further changes to the design, or synthesize the design into a register transfer level file.

Abstract: A programmable input structure for a logic block provides the capability of “bouncing” a logic block input signal back to the interconnect structure of the integrated circuit, and/or to other input terminals of the logic block, without disabling other functions in the logic block. A programmable input multiplexer circuit selects one of the available signals from the interconnect structure, and passes the selected interconnect signal to a logic block. The signal can be disabled within the logic block by programming a bounce multiplexer circuit to select a static value (e.g., power high or ground) instead of the selected interconnect signal. Therefore, the selected signal is safely provided to the interconnect structure and/or another input multiplexer circuit, in addition to the logic block input terminal.

Abstract: A programmable logic block reduces output delay by bypassing a final slave latch when programmed to function as a shift register. The logic block includes memory cells, a multiplexer structure, and a bypass select multiplexer (BSM). The memory cells are coupled in series to form a shift register controlled by a shift clock, each bit including two paired memory cells implementing master and slave latches. Each memory cell drives an input terminal of the multiplexer structure. The BSM drives a select terminal of the multiplexer structure and selects one signal from each pair of the memory cells. The shift clock drives one data input terminal of the BSM. When in shift register mode, the shift clock simultaneously shifts a value in each master latch to the corresponding slave latch and selects a value from one of the master latches. The output path bypasses the slave latch of the selected bit.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.

Abstract: Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. The PLD additionally includes error-correction circuitry that receives each key and associated ECC and performs an error correction before conveying the resulting error-corrected key to a decryptor.

Abstract: An interconnect structure in which “diagonal” and “straight” interconnect lines are interleaved to minimize coupling between adjacent interconnect lines. An interconnect structure for an integrated circuit comprises rows and columns of tiles. Interconnect lines extend at least in part along a first column of the tiles, the interconnect lines including straight and diagonal interconnect lines. A “straight” interconnect line interconnects at least two tiles in the first column, and a “diagonal” interconnect line interconnects a tile in the first column with at least one tile in a different column and row. The interconnect lines are laid out in parallel fashion such that no straight interconnect line is physically adjacent to more than one other straight interconnect line, and no diagonal interconnect line is physically adjacent to more than one other diagonal interconnect line. Optionally, no two physically adjacent interconnect lines drive in the same direction within the first column.

Abstract: In configuring a programmable logic device, first configurable resources of the programmable logic device may be configured as a boot-strap configurator dependent on data in a first portion of configuration memory. After configuring the first configurable resources, data previously stored in a buffer of the programmable logic device may be retrieved to overwrite at least a portion of the configuration memory associated with the boot-strap configurator.

Abstract: A high frequency latch comprising a latch and a plurality of buffers coupled to peak load circuitry produces a peak response at a desired frequency of operation as well as isolating each high frequency latch output of a plurality of outputs to substantially reduce the effects of a kickback signal coupled into the latch output. The peaked load circuitry comprises selectable resistive elements and selectable capacitive elements coupled as a high pass filter to change the bias on a saturation region MOSFET configured as an active load. The high pass filter produces positive feedback on the saturation region MOSFET to increase the bias at high frequencies thereby producing an increased response at a desired operating frequency.

Abstract: A programmable input structure for a programmable logic circuit provides the capability of “fanning out” a selected signal to two or more input terminals of the programmable logic circuit, thereby increasing the routability of the logic block input signals. A logic block for an integrated circuit includes a programmable logic circuit and input multiplexers programmably selecting an input signal to provide to the programmable logic circuit. Also included in the integrated circuit are fan multiplexers that do not drive the programmable logic circuit directly. Instead, the fan multiplexers drive two or more of the input multiplexers that can, optionally, drive other input multiplexers in the same logic block, providing additional selection options among potential input signals. In some embodiments, the fan multiplexers are driven by global and/or regional clock signals. Thus, existing clock distribution structures can be used to provide high fanout input signals to the programmable logic circuit.

Abstract: A method for checking the reset function of an embedded processor is described. First, a check is made to see if a reset “flag” is not set (202) before branching to execute the test routine that initiates the embedded processor's reset (206). The test program sets the flag (204) before initiating the reset. When the processor resets and executes the test program from the beginning again, it determines that the flag was set (202), and it does not execute the reset instructions again.