Abstract: Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.

Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide a count signal associated with external device latency. The count signal is captured responsive to the clock signal.

Abstract: The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

Abstract: Method and apparatus for designing an integrated circuit is described. In an example, the integrated circuit is designed in accordance with timing constraint data. Any logic paths in the plurality of logic paths that have a timing characteristic within a threshold are identified and define a first set of logic paths. Any logic paths in the plurality of logic paths other than those in the first set of logic paths define a second set of logic paths. The integrated circuit is then selectively optimized to reduce power consumption in response to the first set of logic paths and the second set of logic paths. In another example, the integrated circuit is first designed in accordance with timing constraint data. Timing critical logic circuitry is then identified. The integrated circuit is then selectively optimized in response to the timing critical circuitry.

Abstract: Solder ball assembly for a semiconductor device and method of fabricating the same is described. In one example, a solder mask is formed on a substrate having an aperture exposing at least a portion of a conductive pad of the substrate. A solder pillar is formed in the aperture and in electrical communication with the conductive pad. An insulating layer is formed on the solder mask exposing at least a portion of the solder pillar. The exposed portion of the solder pillar is removed to define a mounting surface. A solder ball is formed on the mounting surface in electrical communication with the solder pillar. The solder pillar may include high-temperature solder having a melting point higher than that of the solder ball.

Abstract: Method and apparatus for controlling a processor in a data processing system is described. In an example, the processor is maintained in a halt condition in response to reset information received from the data processing system (200) (e.g., initialization of an integrated circuit having a processor embedded therein). At least one memory resource in communication with the processor is configured. The processor is then released from the halt condition.

Abstract: A system and method are described for securing a configurable system on a chip (CSoC) or other programmable chip design to prevent unauthorized copying. A processor reads instructions from a memory device. The processor reads an identification code from an identification code provider. If no identification code has been previously imprinted on the memory, the processor imprints the provider identification code into the memory. If an identification code is already present, the memory identification code is compared with the provider identification code. If the memory identification code matches with the provider identification code, the processor is allowed to perform the program present on the memory. If the memory identification code does not match with the provider identification code, appropriate security countermeasures are taken. The program and identification code can be further encrypted on the memory for greater security, using the provider identification code as the encryption key.

Abstract: According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

Abstract: Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from the controller to the processor to indicate that the controller is not ready to execute the instruction. Initiation of execution of the instruction by the controller is done while continuing to indicate to the processor that the controller is not ready to execute the instruction.

Abstract: Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plurality of software components, including a library. Hardware component dependency data associated with the library is identified. At least one hardware component is added to the hardware platform in response to the hardware component dependency data.

Abstract: A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.

Abstract: The embodiments of the present invention relate to an improved printed circuit board having additional rows of ground vias to reduce crosstalk in the board. A printed circuit board according to one embodiment of the present invention comprises a first row of vias and a second row of vias, each having a plurality of signal vias. The circuit board also comprises a plurality of rows of vias being coupled to a ground plane between the first row of signal vias and the second row of signal vias. According to one embodiment, the plurality of rows of vias being coupled to a ground plane comprise rows of vias having different sizes. Some of the vias are designed to receive a component, while others are generally smaller and designed to provide a return current path for the signal vias.

Abstract: A memory element structure in a programmable logic device (PLD) reduces power consumption by placing the memory element in a power save mode when the memory element is unused in a user design implemented in the PLD. An exemplary structure includes a multiplexer driving a memory element. A multiplexer control circuit controls the multiplexer, and also drives a clock control circuit for the memory element. When the memory element is used by a user design implemented in the PLD, one of the data inputs is selected to drive the memory element. The controlled functions occur normally in the memory element. When the memory element is not used by the user design, none of the data inputs is selected, an input control signal is intercepted by the clock control circuit, and the controlled functions do not occur in the memory element, reducing the power consumption of the unused memory element.

Abstract: A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.

Abstract: A circuit for generating a clock signal which is frequency aligned with a reference clock signal is disclosed. The circuit comprises a phase detector coupled to receive the reference clock signal and the generated clock signal. A frequency alignment circuit generates an average frequency alignment signal based upon comparison of the phase of a generated pulse train and the phase of a reference pulse train. Finally, an oscillator control circuit is selectively coupled to receive an output of the phase detector based upon the frequency alignment signal from the frequency alignment circuit. The oscillator control circuit generating an oscillator control signal for controlling the frequency of the generated clock signal. A method of generating a clock signal which is frequency aligned with a reference clock signal is also disclosed.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.

Abstract: Clock multiplier circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and the divided values are combined to provide counter stop values representing the numbers of counts in various fractions of the input clock period. A second counter counts from an initial value starting from a first edge of the input clock, and the count is compared in turn to the each of the counter stop values. When the value in the second counter matches one of the counter stop values, a pulse is generated on the output clock signal. Thus, the second counter generates a series of pulses at predetermined times in the input clock period.

Abstract: A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second portion of configuration memory cells that are un-programmed. The programmed and un-programmed configuration memory cells are grouped into voting groups, where each un-programmed configuration memory cell of each voting group is programmed with the identical configuration data as contained within the originally programmed configuration memory cell of each voting group. The logic values of each configuration memory cell of each voting group are monitored by voting circuits, which enforce a triple modular redundancy (TMR) validation policy. The logical validation results are then applied to control points to mitigate PLD configuration memory errors caused by anomalous events such as neutron induced SEUs.

Abstract: Identification of a faulty net in a design implemented on a programmable logic device (PLD). In one approach, configuration data is generated to implement a duplicate circuit of a failing sub-circuit in the design. The PLD is configured with the configuration data that implements the failing sub-circuit and the duplicate circuit, and at least one set of input signals is applied to the sub-circuit and the duplicate circuit. A signal from each net in the sub-circuit is compared on the PLD to a corresponding net in the duplicate circuit. In response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit, the net in the sub-circuit is identified as faulty.