Abstract: Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is selected for input to the analog-to-digital converter (200). Analog information is converted to digital information by the analog-to-digital converter (200), and then such digital information may be stored in data registers (209) for reading out via the boundary-scan controller (1517).

Abstract: Method and apparatus for a system monitor (20) embedded in a programmable logic device (10, 50, 60) are described. The system monitor (20) includes a dynamic reconfiguration port interface (205) for configuring or reconfiguring the system monitor (20) during operation thereof. The system monitor (20) includes an analog-to-digital converter (200) which is reconfigurable responsive to input via a dynamic reconfiguration port (201).

Abstract: Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.

Abstract: Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.

Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Abstract: A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differential multiplexer; and a programmable driver circuit configured to boost an output current of the programmable driver circuit at selected frequencies and to convert two phase full CMOS differential signal outputs of the differential multiplexer to a second small signal differential signal.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

Abstract: A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.

Abstract: Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: A method for designing an integrated circuit having both fixed logic and programmable logic components. An intended set of applications for the integrated circuit is first identified. In addition, for each of the intended set of applications, the logic requirements are identified. An approximate number of configurable logic blocks and at least one fixed logic circuit are selected that, when combined to operate cooperatively, meet a substantial portion of the logic requirements and the logic functions of the intended set of applications. The method also involves designing the integrated circuit with the approximate number of configurable logic blocks arranged and interconnected to form a fabric that surrounds an opening, and inserting the at least one fixed logic circuit into the opening in the fabric. In addition, the method involves adding logic to the integrated circuit that interfaces the at least one fixed logic circuit to the fabric and input/output circuitry.

Abstract: A hybrid interface apparatus including a fixed base including a contact-locking structure supporting several spring-based contact members, and a nesting member slidably positioned over the fixed base and having a central test area that includes an array of through-holes that are aligned with upper ends of the contact members. To facilitate testing of ICs including both relatively low-speed general-purpose I/O structures and new high-speed I/O structures, the contact members mounted on the contact structure include both low-cost, relatively high-inductance contact members for facilitating communication with the general-purpose I/O structures of the IC, and relatively expensive, low-inductance contact members for facilitating high-speed communications with the high-speed I/O structures of the IC.

Abstract: Binary hysteresis equal comparator circuits and methods. An equal comparator does not indicate an equal condition until the two binary input values are exactly the same. However, after the two binary input values first become equal, a window of variation comes into effect, within which the first of the two values is allowed to vary while the circuit continues to report an equal condition. This window can extend only above the equal condition, only below the equal condition, or both above and below the equal condition. The width of the window is determined by providing one or two predetermined constant values, a first constant defining the amount of hysteresis provided above the second value, and a second constant defining the amount of hysteresis provided below the second value. Related methods are also described of performing equal comparisons while providing binary hysteresis.

Abstract: A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.

Abstract: A balanced peak detector circuit adjusts differential voltage signals. In one embodiment, the peak detector uses competing current paths to provide a charging current to a storage capacitor. The charge on the storage capacitor is used to adjust either a transconductance or a transimpedance circuit. An offset current can be used to adjust the charge stored on the capacitor to change a peak-to-peak output voltage from the transimpedance circuit. In one embodiment, the offset current can be adjusted using an adjustable current source. A discharge circuit has been describe that allows a discharge of the capacitor to be controlled.

Abstract: A ring oscillator with a plurality of delay stages having selectable active loads for selecting an R-C time constant that defines a delay through the delay stage. The ring oscillator oscillation frequency is a function of the selected R-C time constant, a selectable bias level, and the number of delay stages in the ring oscillator. In one embodiment, a MOSFET device gate-to-source capacitance is used with at least one selectable resistive device to form the R-C time constant. In an alternate embodiment, a plurality of parallel coupled resistive devices and parallel coupled capacitive devices are selectively coupled to the active load circuit to set the delay through the delay stage. The resistive devices are formed to be one of a resistor configured MOSFET device and a traditional resistive element. The capacitive devices are formed to be one of a capacitor configure MOSFET device and a traditional capacitive element.

Abstract: A high speed phase detector circuit operating at a clock speed equal to one-half an input data rate (i.e. a half-rate clock) provides phase information and transition information from incoming serial data. The high speed phase detector circuit samples the incoming serial data on both the rising edge and falling edge of the half-rate clock to provide equivalent full high speed data rate sampling. The high speed phase detector circuit generates a delay between the phase information and the transition information. The phase information is produced in a first bit period and the transition information is produced in a second bit period relative to the first bit period.

Abstract: The invention relates to a method for placing design components of an integrated circuit. A first site is selected. Other sites that are at maximum distances from already used sites may be selected. Components that have minimum connectivity to already placed components are selected. These components are used for preplacement. Preferably, the number of preplaced components is small. The rest of the design components are placed. An overlap ratio is computed. If the overlap ratio is above a predetermined value, the result is unplaced and additional components are preplaced. Another placement is performed. Overlap ratio is again computed. The steps of unplacing, adding preplaced components and computing overlap ratio are repeated until the overlap ratio falls below the predetermined value.