Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

Abstract: A system (20) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array (10) having a programmable fabric (12). The system can include a predefined interface (42) between an embedded microprocessor and the programmable fabric as well as a translator (25) enabling a single hardware description language to define the system including both the microprocessor and the programmable fabric.

Abstract: A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the devices that are part of the transaction. Additionally, the bus frequency is set according to the length of the bus between the devices that are a part of the transaction and, correspondingly, the expected amount of impedance there between. As a part of the present invention, a master seeking bus resources to initiate a transaction generates a bus request and a destination address to the bus arbiter so that it may determine a corresponding bus frequency in advance. Thereafter, the bus arbiter sets the bus frequency to a value that corresponds to the transaction that is about to take place thereon. Next, the bus arbiter issues a grant signal to enable the master to use the bus. Each slave device for a transaction then generates or receives sample cycle signals indicating when a signal should be read on the bus.

Abstract: Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.

Abstract: Method, apparatus, and computer readable medium for translating an electronic design of an integrated circuit into circuit description language is described. The electronic design includes a plurality of circuit descriptions representing behavior of circuit elements. A circuit description template is associated with a circuit description of the plurality of circuit descriptions. The circuit description template includes a first portion for fixed attributes of the circuit description and a second portion for variable attributes of the circuit description. One or more text processors are associated with the circuit description template. Variable attributes of the circuit description are related to the second portion of the circuit description template to produce a data structure. The circuit description template is processed using the one or more text processors with the data structure as parametric input.

Abstract: Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out.

Abstract: Battery management can be advantageously integrated into a programmable logic device (PLD). Specifically, by using a programmable battery controller provided on the PLD, the user can make a decision regarding battery choice much later in the design process, reduce the inventory of batteries associated with the system/product, increase the life of the batteries, and upgrade to the newest technology battery at the user's discretion. The battery controller can be implemented on any type of PLD, e.g., an FPGA, potentially requiring battery management for critical circuits.

Abstract: A balanced clock tree has a coaxial structure when a piece of the tree is viewed in cross-section. A plate is capacitively coupled to the inner conductor that runs down the center of the coaxial structure. This plate is usable to AC couple into the clock signal being propagated down the clock line. A programmable structure is disclosed for doing this whereby the clock signal is capacitively coupled from the clock line onto the input lead of a latch. The latch recreates the clock signal. The latch drives the recreated clock signal onto a local clock conductor. The structure is programmable in that it either couples the clock signal onto the local conductor or not depending on the state of a configuration bit in a memory cell of the programmable structure. In one embodiment, the clock tree can be tapped without substantially affecting signal propagation characteristics of the clock tree.

Abstract: Lookup table (LUT) circuits can optionally be configured as two or more smaller LUTs having independent input signals. A LUT circuit includes a tristate buffer circuit coupled between first and second multiplexer stages. The data input of the tristate buffer circuit is provided as a first output signal from the LUT circuit. The output of the second multiplexer stage provides the second LUT output signal. The tristate buffer circuit can include a tristate buffer with a pullup and a pulldown on the output terminal. To configure the circuit as a single LUT, the buffer is enabled (tristate disabled), and both the pullup and pulldown are turned off. To configure the circuit as two separate LUTs, the buffer is tristated and either the pullup or the pulldown is enabled. Additional multiplexer stages and tristate buffer circuits can be included to enable the division of the circuit into larger numbers of LUTs.

Abstract: An inductive amplifier having a feed forward boost is provided, thereby improving the gain of the inductive amplifier at frequencies greater than 1 GigaHertz. The inductive amplifier includes a feed-forward boost circuit coupled to intermediate nodes of an inductive amplifier circuit, whereby the feed-forward boost circuit generates boost currents that are added to the currents of the inductive amplifier circuit. In one embodiment, the feed-forward boost circuit includes a boost current supply, a first boost transistor coupled between the current supply and a first intermediate node of the inductive amplifier circuit, and a second boost transistor coupled between the current supply and a second intermediate node of the inductive amplifier circuit. In one embodiment, the first and second boost transistors and the inductive amplifier circuit are controlled by the same differential input signals.

Abstract: Described are methods and circuits of programming a programmable logic device with encrypted configuration data using one or more secure decryption keys. Configurable resources within PLDS in accordance with one embodiment are divided into first and second collections of configurable interconnect resources separated by a collection of switches. One collection of resources has access to one or more decryption keys required to decrypt the encrypted configuration data. The switches protect the proprietary keys by providing a secure boundary around the portion granted key access during the decryption process. Closing the switches after configuration clears user memory to prevent users from accessing stored versions of the proprietary keys.

Abstract: Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.

Abstract: A phase adjustment module in a voltage controlled oscillator (VCO) samples a VCO oscillation to detect changes in the oscillation frequency and produces a corresponding correction voltage that is feedback to the VCO input to correct the frequency change. A plurality of sampling modules, each formed to start sampling at a different point on the oscillation cycle, charge a sampling module capacitor over the period of a full oscillation cycle. The samples are coupled to a low pass filter to produce a running average of all the samples. The charge on each capacitor is coupled to a first input of a plurality of operational amplifiers and the running average is coupled to a second input. The summed output of the operational amplifiers is substantially equal to a difference between the running average and a voltage representing the instantaneous time change or phase change of the oscillation frequency.

Abstract: A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.

Abstract: A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

Abstract: A method for reducing leakage power in a system comprises determining the static probability for a signal in the system. If the static probability of the signal is in a high power range, then the signal is modified such that the static probability of the modified signal is in a low power range, and such that functionality of the system is not affected. In some embodiments, where the signal is a digital signal, modifying the signal comprises inverting the signal. In some embodiments, where the system comprises a programmable logic device, modifying the signal has no area or performance penalty.

Abstract: Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Abstract: Methods of implementing routing matrices for programmable logic devices (PLDs). Each method includes generating a seed matrix, a distribution matrix, adjustment values for the distribution matrix, and a routing matrix pattern. The seed matrix and distribution matrix are implemented according to a set of rules that define valid matrices. The routing matrix is then implemented by applying the routing matrix pattern to provide programmable interconnections between input and output terminals of the routing matrix. Each signal value in the routing matrix pattern corresponds to one of the input terminals, and each row of signal values in the routing matrix pattern corresponds to a set of the input terminals programmably coupled to a different one of the output terminals. By adding additional columns of sub-matrices to an existing distribution matrix, an existing routing matrix can also be expanded to accommodate a larger number of input signals.