Patents Assigned to Xilinx, Inc.
  • Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device
    Patent number: 6925583
    Abstract: According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: August 2, 2005
    Assignee: Xilinx, Inc.
    Inventors: Arthur H. Khu, Conrad A. Theron, Farshid Shokouhi, Pushpasheel Tawade
  • Integrated circuit and method of reading data from a memory device
    Patent number: 6925014
    Abstract: A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOS. A blockRAM based zero-cycle latency read FIFO is also described.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: August 2, 2005
    Assignee: Xilinx, Inc.
    Inventors: Thomas E. Fischaber, Scott J. Campbell
  • Counter-based phase shifter circuits and methods with optional duty cycle correction
    Patent number: 6924684
    Abstract: Phase shifter circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and a delay value is determined based at least in part on the counted value. In some embodiments, the delay value has a maximum value that depends on the counted value. The delay value is provided to a second counter, which counts from zero to the delay value and generates a pulse one delay value after the beginning of the input clock period. A third counter running at the same clock rate generates a pulse after an additional delay. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle. Some circuits also perform a duty cycle correction.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: August 2, 2005
    Assignee: XILINX, Inc.
    Inventor: Andy T. Nguyen
  • Method and system for device-level simulation of a circuit design for a programmable logic device
    Patent number: 6922665
    Abstract: A method and system for simulating a circuit design for a programmable logic device (PLD) at the device level. The same configuration data that is used to configure a PLD is used to generate objects that represent configurable logic elements of the PLD. During simulation, events are generated based on changes in output signal states of the objects. Each event includes an input signal state and identifies an object to which the input signal is to be applied. Since configurable logic elements are simulated, for example, lookup tables, instead of logic gates, fewer events need to be generated and processed than in a conventional simulator. In another embodiment, the system supports an interface that allows tools to interface with the simulator in the same manner as the tools interface with a PLD.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: July 26, 2005
    Assignee: Xilinx, Inc.
    Inventors: Steven A. Guccione, Scott P. McMillan, Brandon J. Blodget
  • Reconfiguration of a programmable logic device using internal control
    Patent number: 6920627
    Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: July 19, 2005
    Assignee: XILINX, Inc.
    Inventors: Brandon J. Blodget, Scott P. McMillan, Philip B. James-Roxby, Prasanna Sundararajan, Eric R. Keller, Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck
  • Methods of testing for shorts in programmable logic devices using relative quiescent current measurements
    Patent number: 6920621
    Abstract: Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: July 19, 2005
    Assignee: Xilinx, Inc.
    Inventors: Shahin Toutounchi, Erik V. Chmelar, Robert W. Wells
  • Configurable processor system
    Patent number: 6920551
    Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 19, 2005
    Assignee: Xilinx, Inc.
    Inventor: Eric J. Crabill
  • Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice
    Patent number: 6917219
    Abstract: The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: July 12, 2005
    Assignee: Xilinx, Inc.
    Inventor: Bernard J. New
  • Method and apparatus for processing data within a programmable gate array using fixed and programmable processors
    Publication number: 20050149695
    Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.
    Type: Application
    Filed: February 17, 2005
    Publication date: July 7, 2005
    Applicant: Xilinx, Inc.
    Inventors: Stephen Douglass, Ahmad Ansari
  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Publication number: 20050149777
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 7, 2005
    Applicant: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael Hart, Zicheng Ling, Steven Young
  • Memory cells enhanced for resistance to single event upset
    Patent number: 6914804
    Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: July 5, 2005
    Assignee: Xilinx, Inc.
    Inventor: Austin H. Lesea
  • Methods of utilizing noise cores in PLD designs to facilitate future design modifications
    Patent number: 6915503
    Abstract: Methods of using “noise cores” in a PLD design. “Noise cores” are pre-developed blocks of logic included in a PLD design for the purpose of creating noise in other circuits also implemented in the PLD. By gradually increasing the level of noise created by the noise core, the noise sensitivity of the user circuit can be determined. Also, by ensuring that the user circuit functions properly when combined with the noise core, a designer can have confidence that unmodified portions of the user circuit will still function properly when the user circuit is modified. In some embodiments, once the user circuit has been qualified with the noise core operational, the noise core is disabled prior to including the PLD design in a system. Because the user circuit is proven to withstand a certain level of noise, future additions to the design do not necessarily require re-qualification of the user circuit.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 5, 2005
    Assignee: Xilinx, Inc.
    Inventor: Austin H. Lesea
  • Structure for reducing leakage current in submicron IC devices
    Patent number: 6914449
    Abstract: A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters or logic gates and ground or power. NMOS and PMOS transistors are added to selected buffers comprised of two inverters in series. The PMOS transistor is connected between the first inverter and power and the NMOS transistor is connected between the second inverter and ground. The added transistors are controlled by a memory cell to be on when the buffer is being used and off when the buffer is unused. Alternatively, no PMOS transistor is added and an existing PMOS transistor of the first inverter is manufactured to sit in a Vgg well. The same techniques are employed with selected buffer pairs and logic gates.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: July 5, 2005
    Assignee: Xilinx, Inc.
    Inventor: Alireza S. Kaviani
  • Counter-based clock doubler circuits and methods
    Patent number: 6914460
    Abstract: Clock doubler circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is divided by two to provide the number of counts in half of the input clock period. The divided value is provided to a second counter that counts from zero to the divided value. Thus, the second counter generates a pulse halfway through the input clock period. Other counters running at the same clock rate can be used to generate pulses at other times in the input clock cycle, as desired. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: July 5, 2005
    Assignee: Xilinx, Inc.
    Inventor: Andy T. Nguyen
  • System and method for runtime reallocation of PLD resources
    Patent number: 6915518
    Abstract: A system and method for allocating resources of programmable logic devices (PLDs) according to activity level. In various embodiments, the activity levels of functions implemented on the PLDs are monitored. When decreasing and/or increasing activity levels are detected, the PLD resources are reallocated between the various functions in proportion to the decreasing and/or increasing activity levels.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: July 5, 2005
    Assignee: Xilinx, Inc.
    Inventor: Neil G. Jacobson
  • Programmable logic device with dynamic DSP architecture
    Publication number: 20050144210
    Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 30, 2005
    Applicant: Xilinx, Inc.
    Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
  • Applications of cascading DSP slices
    Publication number: 20050144215
    Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 30, 2005
    Applicant: Xilinx, Inc.
    Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
  • Mathematical circuit with dynamic rounding
    Publication number: 20050144213
    Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M?1) and 2(M?1)?1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 30, 2005
    Applicant: Xilinx, Inc.
    Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
  • Programmable logic device with cascading DSP slices
    Publication number: 20050144212
    Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 30, 2005
    Applicant: Xilinx, Inc.
    Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
  • Wireless programmable logic devices
    Publication number: 20050143022
    Abstract: A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.
    Type: Application
    Filed: February 8, 2005
    Publication date: June 30, 2005
    Applicant: Xilinx, Inc.
    Inventors: Bernardo Elayda, Brian Erickson