Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area.

Abstract: A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device arranged in the order in which the devices are chained in the system. The device identification codes are then used to automatically retrieve device specifications from a central database. When no identification code is provided from the device, or the database fails to include specifications for a particular device, the user is prompted to enter minimum information or specifications necessary to carry out communications with the device. After device specifications are entered for each device, the user is prompted to enter configuration data, which is automatically matched to its associated device, and compared for consistency with the device specifications.

Abstract: A system and method for testing a parameterizable logic core are provided in various embodiments. A test controller is configured and arranged to generate a set of random parameter values for the logic core. A netlist is created from the parameterized logic core, and circuit behavior is simulated using the netlist. In other embodiments, selected parameter values are optionally weighted to increase the probability of generating those values, and the parameter set is cloned and mutated when simulation fails.

Abstract: Described are programmable logic devices with configuration memory cells that function both as RAM and ROM. A PLD incorporating these memory cells to store configuration data can be mask-programmed with a customer design, rendering the PLD an application-specific integrated circuit (ASIC). The mask programming can be selectively disabled, in which case each configuration memory cell behaves as a static, random-access memory (SRAM) bit. In this mode, a PLD employing these dual-mode memory cells behaves as a reprogrammable PLD, and can therefore be tested using generic test procedures developed for the PLD. The dual-mode memory cells thus eliminate the burdensome task of developing application-specific test procedures for designs ported from a PLD. As an added benefit, in the ROM mode these memory cells are not susceptible to radiation-induced upsets, so for example, PLDs incorporating these memory cells are better suited for aerospace applications than conventional SRAM-based PLDs.

Abstract: A method of producing a wirebond ball grid array package is described. The method comprises the steps of importing a master pinlist to a computer program, importing a bonding diagram to the computer program, and verifying, by the computer program, substrate artwork against the master pinlist and the bonding diagram. A method of producing a wirebond ball grid array package according to an alternative embodiment comprises the steps of importing a master pinlist to a computer program, importing substrate artwork to the computer program, and verifying, by the computer program, a bonding diagram against the master pinlist and the substrate artwork. Finally, a system for verifying substrate artwork comprises means for importing a master pinlist to a computer program, means for importing a bonding diagram to the computer program, and means for verifying, by the computer program, the substrate artwork against the master pinlist and the bonding diagram.

Abstract: A system and method for diagnosing a software system within a remote electronic device using a network is provided. A diagnostic controller controls diagnostics of the software system by instructing the remote electronic device to replace a selected software component of the software system with a diagnostic software component. The diagnostic software component has equivalent operational characteristics as the selected software component and includes trace logic that collects diagnostic data while operating with the software system. An analysis routine analyzes the diagnostic data and recommends a corrective measure for the software system.

Abstract: According to one embodiment, a locally regulated circuit regulates current flows (IREG and IRG) through the operation of a current mirror (334, 332, 326). The regulated current flows are used to self-generate a common mode voltage (V422) at node (322) and to produce the required bias signals through input stage (302 and 308) and output stage (314 and 316) in response to data input signals (D and D-complement). Cancellation of common mode voltage variation is further enhanced by generating a supplemental current in response to an error signal generated by comparing a desired common mode voltage (VCM) to the actual common mode voltage at node (322). The supplemental current conducted by either of loads (310 and 312) serves to regulate the common mode voltage at node (322).

Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.

Abstract: Various approaches for converting configuration data for programmable circuits are disclosed. In one embodiment, a first configuration bitstream is provided. The first configuration bitstream has a format compatible with a first protocol for communicating with and configuring the programmable circuit. A second protocol is selected for communicating with and configuring the programmable circuit, and the first configuration bitstream is converted to a second configuration bitstream. The second configuration bitstream has a format compatible with the second protocol. The programmable circuit is configured with the second configuration bitstream.

Abstract: A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and to generate a second plurality of timing signals when the width of the parallel input data is of a second multiple. The parallel to serial module is operably coupled to convert the parallel input data into serial output data based on the first or second plurality of timing signals.

Abstract: Described are area-efficient non-volatile memory systems. Non-volatile memory cells in these systems include only one transistor, two fewer than conventional non-volatile memory cells, and reduced interconnect. The simplicity of the memory cells reduces memory-system area, improves manufacturing yield, and consequently reduces cost. New program, erase, and read methodologies have been developed for use with the simplified memory cells.

Abstract: A frequency-divider circuit performs a division operation using a divisor that can include a fraction. In one such embodiment, a first divider module includes a divider circuit that operates to divide the frequency of an input clock signal and a phase-quadrature circuit. The first divider module generates a first-divider-output signal having periodic signals with regular phase displacement therebetween and a common period that is an integer multiple of the clock signal. Using this first-divider-output signal, a second divider module performs another divide operation and is clocked as a function of a delay effected by at least one of the periodic signals. The present invention is useful in a wide variety of applications including applications having a high frequency clock source that cannot tolerate excessive loading or jitter attributable to a divider circuit.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as “programmed”, and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as “erased”, and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the “erased” value is included in each word.

Abstract: The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. Because the frequencies are spread in 0.5 MHz increments, only three frequencies are included in any 1 MHz window. As a result, ? of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency.

Abstract: A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.

Abstract: Clock doubler circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is divided by two to provide the number of counts in half of the input clock period. The divided value is provided to a second counter that counts from zero to the divided value. Thus, the second counter generates a pulse halfway through the input clock period. Other counters running at the same clock rate can be used to generate pulses at other times in the input clock cycle, as desired. The pulses from the counters are used in combination with the input clock signal to provide output clock edges at predetermined times during the input clock cycle.

Abstract: Described is a power multiplexer that alternately transmits zero, supply voltage, and a relatively high voltage to a common output node. The power multiplexer includes low-impedance voltage switches, at least one of which includes a well-voltage select circuit. The well-voltage select circuit adjusts the well bias on a power-switching transistor, and consequently protects the power-switching transistor from damage caused by gate breakdown and forwarding biasing of the well.