Abstract: An incremental placement method uses a set of connections to optimize and a set of movable design objects. The movable design objects are unplaced. A plurality of anchoring connections is associated with the movable design objects. A set of weights is associated with the set of connections to optimize and the plurality of anchoring connections. An objective function is constructed using the set of connections to optimize, the plurality of anchoring connections, and the set of weights. The objective function is minimized to obtain a placement of the movable design objects.

Abstract: The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit for an input pad. In one embodiment, the output buffer is capable of injecting a constant onto a pad during reconfiguration of a configurable system logic circuit. The present invention also provides a circuit for generating a programmable data propagation delay, thereby guaranteeing zero hold time for an arbitrary input register. Zero hold time is accomplished by allowing the user to optimally characterize clock delay to a given input/output circuit. The present invention also provides fast switching between input pads, thereby minimizing data propagation delay between the input pads. Additionally, the present invention reduces time spent in production product test by facilitating the testing of multiple routes with one test configuration.

Abstract: A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.

Abstract: A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

Abstract: A method for channel bonding begins when a master transceiver receives a channel bonding sequence. The process continues with the master transceiver generating a channel bonding request and transmitting it and channel bonding configuration information to the slave transceiver. The process continues with each slave receiving the channel bonding sequence, the channel bonding request and the channel bonding configuration information. The process continues as each slave processes the channel bonding request and the channel bonding sequence in accordance with the channel bonding configuration information to determine individual slave channel bonding start information. The process continues as the master processes the channel bonding sequence in accordance with the channel bonding configuration information and the channel bonding request to determine master channel bonding start information.

Abstract: A ring oscillator with a plurality of delay stages having selectable active loads for selecting an R-C time constant that defines a delay through the delay stage. The ring oscillator oscillation frequency is a function of the selected R-C time constant, a selectable bias level, and the number of delay stages in the ring oscillator. In one embodiment, a MOSFET device gate-to-source capacitance is used with at least one selectable resistive device to form the R-C time constant. In an alternate embodiment, a plurality of parallel coupled resistive devices and parallel coupled capacitive devices are selectively coupled to the active load circuit to set the delay through the delay stage. The resistive devices are formed to be one of a resistor configured MOSFET device and a traditional resistive element. The capacitive devices are formed to be one of a capacitor configure MOSFET device and a traditional capacitive element.

Abstract: A transmit line driver with selectable slew rates and a common mode idle state comprises a capacitor array of selectable capacitors coupled between a line driver and a pre-driver wherein a slew rate may be selected by the selectable capacitors. A common mode idle state is provided by coupling a selectable switch (MOSFET in the described embodiment) to a mirror device that provides a bias current to the pre-driver wherein, when the bias current is removed by the switch, the pre-driver produces an output signal that is equal to the supply voltage for the circuit. Accordingly, a differential pair of the line driver are both biased on and provide a common mode idle state. The common mode idle state is equal to one half of an output signal magnitude for a logic one.

Abstract: An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Abstract: Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing continues by scrambling the input code word in accordance with the 1st scrambling protocol to produce a 1st scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1st scrambled code word based on the scrambling remainder. The process continues by combining the scrambled partial code word with the portion of the 1st scrambled code word to produce the transmit encoded output data.

Abstract: For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

Abstract: A test circuit is included in an IC wafer for testing the reliability of ICS under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

Abstract: Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.

Abstract: A method for programming a semiconductor element in a semiconductor structure such as an IC involves reducing the backside thickness of the substrate and directing an energy beam through the backside at an opaque component of the semiconductor element. A support structure mounted on the semiconductor structure provides support during and after the thinning operation. Alternatively, the substrate can be thinned only under the semiconductor element, leaving the rest of the substrate thick enough to maintain structural integrity. The energy beam heats the opaque component. The prior thinning operation minimizes heat dissipation away from the semiconductor element, so that dopant diffusion occurs, changing the electrical characteristics of the semiconductor element. By modifying selected elements in this manner, a semiconductor structure can be permanently programmed, even if it does not include non-volatile memory. Additionally, security is enhanced since the programming leaves no visible signs.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

Abstract: Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.