Abstract: A glitchless T length pulse is generated by coupling a trigger signal and the latched output of a counter. The trigger signal initiates the start of the T length pulse, and the latched output of the counter initiates the end of the T length pulse after counting up a duration of T from a number of clock cycles of a clock signal. Latching the output of the counter prior to terminating the T length pulse eliminates glitches. Accuracy of the count determining the length of the T length pulse may be increased by latching the trigger signal with the clock signal to generated a synchronized trigger signal, and using the synchronized trigger signal to initiate the T length pulse.

Abstract: A linear actuator with dual direction self-locking mechanism which can lock the load if linear actuator at the position where power stop. The self-locking mechanism includes a transmission device, an actuating unit and a spring. This mechanism can unlock the linear actuator automatically without producing extra load during the operation of the linear actuator, which can be applied to linear actuator with both pull and push load.

Abstract: A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.

Abstract: A method for accurate testing of the output voltage of an integrated circuit comprises enabling a differential voltage comparator on the integrated circuit to be tested. One input to the differential comparator is set to a reference voltage, and the other input is coupled to a node to be tested. A current load is injected at the node, and the output of the voltage comparator can be used to determine if the integrated circuit performs within the specifications set by a manufacturer.

Abstract: A method (300) of generating a simplified netlist using bus information includes the steps of identifying (302) nets that form buses in a netlist and identifying (304) instances of a same type that connect to the identified nets via pins of the same name to form at least one set of instances. The method further includes the step of replacing (308) at least one set of instances with at least a single arrayed instance if each net in a bus is connected to exactly one of the same type of instance via a pin of the same name and the step of deleting the nets forming the arrayed instance from the netlist and replacing (314) the nets with a corresponding bus.

Abstract: A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer.

Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.

Abstract: A method of designing an integrated circuit using a general purpose programming language can include identifying (105) a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling (110) the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined (115) and access to the modeled global memory can be scheduled (120). The programmatic design can be translated (125) into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

Abstract: A method for multiple memory aliasing for a configurable system-on-a-chip, including executing code from an internal memory, locating a configuration program in the internal memory, disabling the internal memory alias, and jumping to a secondary initialization routine, is disclosed.

Abstract: A tunable narrow-band filter that includes a sigma-delta modulator. In one embodiment, a conventional DC canceler is modified to include a re-quantizer in the feedback loop in the form of a ?? modulator. In another embodiment, a digital receiver employs a processing chip, such as an FPGA, that includes a ?? modulator to requantize oversampled control signals in the digital receiver. In still another embodiment, a wide-bandwidth sigma-delta loop has a tunable center frequency.

Abstract: A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.

Abstract: On-the-fly reconfiguration of a secured CPLD. In one embodiment, a CPLD includes a novel security circuit that provides two different security control signals: an EEPROM/SRAM security signal and an EEPROM security override signal. The EEPROM/SRAM security signal prevents reading from both the EEPROM and the SRAM, and also prevents writing to the EEPROM. The EEPROM security override signal enables reading and writing for the EEPROM even when otherwise disabled by the EEPROM/SRAM security signal, but is active only when a specific set of conditions are met. These conditions can include, for example, the application of a sufficiently long erase pulse to the EEPROM array. Thus, the security on the EEPROM array is overridden only after the configuration data set stored in the EEPROM array has been erased. Reading from the SRAM is not enabled by the EEPROM security override signal. Therefore, the configuration data set is not compromised.

Abstract: Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations.

Abstract: A clock control circuit routes one of a plurality of clock signals to a clock output node, and employs an asynchronous state machine to switch between clock signals without introducing glitches. To switch from a first to a second clock, the control circuit samples the logic level of the first clock signal to obtain a sampled logic level. The control circuit then provides a constant version of the sampled logic level on the clock output terminal until the second clock signal transitions to the sampled logic level, at which point the control circuit routes the second clock signal to the clock output node.

Abstract: A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.

Abstract: Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.

Abstract: Method and apparatus for determining power dissipation for an integrated circuit using computer simulation is described. More particularly, the integrated circuit is divided into cells, and one or more nodes are identified within each of the cells. A capacitive load value is ascribed to each of the nodes, and code is generated to track charges in state of each of the nodes. A total for changes in state for each node is divided by simulation time to determine a switching frequency. Using switching frequency, capacitive load and source voltage, dynamic power dissipation for each node may be determined. By summing dynamic power dissipation for all said nodes, total dynamic power dissipation may be determined.

Abstract: A transmit line driver with selectable slew rates and a common mode idle state comprises a capacitor array of selectable capacitors coupled between a line driver and a pre-driver wherein a slew rate may be selected by the selectable capacitors. A common mode idle state is provided by coupling a selectable switch (MOSFET in the described embodiment) to a mirror device that provides a bias current to the pre-driver wherein, when the bias current is removed by the switch, the pre-driver produces an output signal that is equal to the supply voltage for the circuit. Accordingly, a differential pair of the line driver are both biased on and provide a common mode idle state. The common mode idle state is equal to one half of an output signal magnitude for a logic one.