Abstract: A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.

Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.

Abstract: A light curtain safety system for a semiconductor device handler that includes a programmable control unit and a robot mechanism that is selectively operated in response to signals generated by the control unit. The light curtain safety system includes an apparatus for generating a light curtain such that accessing the robot mechanism requires breaking the light curtain. The light curtain safety system detects an operating state of the semiconductor device handler using signals generated in the control unit, and allows de-activation of the light curtain apparatus only when operating state of the semiconductor device handler is in a predetermined “safe” operating state. When the light curtain apparatus is active and the light curtain is broken, the light curtain safety system causes the semiconductor device handler to terminate power flow to the robot mechanism.

Abstract: A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the ripple counter circuit alternates between two states. In the first state, the bits all toggle from their initialization values to new values. In the second state, the circuit operates in the same fashion as the user mode. Therefore, the ripple counter circuit counts by one, returning all of the bits to their initialization values. This capability significantly simplifies the testing process, particularly for long ripple counters. Some embodiments of the invention include various control circuits coupled to provide an internal clock signal and/or an initialization signal.

Abstract: The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources and ensure the correct initialization of the CSoC. The CSoC leverages an on-chip central processing unit (CPU) to control the configuration process of the configurable system logic (CSL). Advantageously, the CSL configuration memory cells as well as other programmable locations in the CSoC are addressable as part of a system bus address space. The system bus is a multi-use structure that can be used for both configuring and reading of memory cells. In this manner, the CSoC optimizes system resources.

Abstract: A die having a bypass capacitor is stacked on another die having an active circuit. The active circuit draws a spike of current, for example, during a switching period of a voltage on its output lead from one digital logic level to another digital logic level. The bypass capacitor provides a portion of the spike of current through a conductive plug that extends from a plate of the bypass capacitor to a power lead of the active circuit. The length of the conductive plug is reduced by extending the conductive plug from the bypass capacitor to the active circuit orthogonally to the planar orientation of the dice. Reducing the length of the conductive plug reduces the resistance and inductance of the conductive plug and, in turn, reduces the drop in voltage between the voltage on the bypass capacitor and the voltage on the power lead of the active circuit.

Abstract: A systematic method for calculating future cost is disclosed. Pre-routing is performed from a source node to other nodes through a series of neighboring nodes. At each node in the pre-routing, the cumulative routing cost and Manhattan distance are calculated. This cumulative routing cost is used as a new future cost for a specific distance if it is lower than or there is no existing future cost for that distance. A table can be used to store the future cost data. During routing, the recorded future cost is added to the cumulative cost of a node to help guide the routing, improving router run-time.

Abstract: A test oscillator circuit separately measures the signal propagation delay for both rising and falling edges through one or more multi-input combinatorial logic circuits. A number of components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component passes signal edges to a subsequent component in the ring, so the oscillator produces an oscillating test signal in which the period relates to the delays through the components. In some embodiments, the multi-input combinatorial logic circuits emulate tri-state buffers. These embodiments characterize the speed at which these logic circuits enable and disable signal paths.

Abstract: Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.

Abstract: Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.

Abstract: A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOs. A blockRAM based zero-cycle latency read FIFO is also described.

Abstract: A method of outputting data from a FIFO incorporated in an integrated circuit generally determines whether input data is valid during a first clock cycle. The method then outputs data from a plurality of output barrel slots during a second clock cycle. Data is then shifted from predetermined upper barrel slots to predetermined output barrel slots during second cycle based upon a barrel count. Finally, data is shifted into the FIFO during said second cycle based upon the barrel count. A new barrel count of valid data in the FIFO can then be determined. Circuitry for implementing the embodiments of the invention is also disclosed.

Abstract: Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.

Abstract: Disclosed is a DC thermal energy generator for heating localized regions of an integrated circuit. The integrated circuit includes a pair of static circuits whose outputs are shorted, and are in contention. Contention causes current to flow through the circuits, generating heat. Integrated-circuit temperatures can be varied by turning on more or fewer thermals energy generators. The thermal resistance of a, packaged integrated circuit is computed using a well-known relationship integrated circuit's measured temperature, power consumption, and the ambient temperature.

Abstract: Described are power-on reset methods and circuits for resetting and subsequently enabling integrated circuits in response to applied power. A POR circuit in accordance with one embodiment is capable of operating at exceptionally low temperatures and supply voltages, and is relatively tolerant to process variations. The POR circuit compares a band-gap reference signal to a temperature-compensated reference signal that varies in inverse proportion to temperature. The temperature-compensated reference signal extends the useful temperature range of the POR circuit.

Abstract: A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a multiplexer that is configured to receive the input signals (including the carry input signal) and provides an output signal that can be routed as the carry output signal. A driver circuit can be coupled to the output terminal of the multiplexer, thereby improving the drive of the single path. A separate path is provided in parallel with the first multiplexer path, thereby enabling the carry input signal to be applied to exclusive OR gates within the CLB slice, or to be provided as an intermediate carry output signal. The single path provides a relatively fast and consistent manner of routing the carry input signal through the CLB slice as the carry output signal. The first and second paths accommodate a carry initialization signal as well as an intermediate carry input signal.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: Method and apparatus for thermally conditioning a microchip is described. The microchip (104) is thermally conditioned responsive to a temperature target over an interval of time. A diode voltage of a diode (503) of the microchip (104) is measured from which diode temperature is determined. The diode temperature is compared with the temperature target to determine a temperature error. This thermal conditioning may be repeated, where interval times are adjustable responsive to temperature error, until a stabilization band (401) is reached. Because a diode (503) of the microchip (104) is used, junction temperature, as opposed to external surface temperature of the microchip package, is obtained. Accordingly, a thermocouple attached to the external surface of the microchip is not needed.

Abstract: An integrated circuit (IC) is disclosed having circuitry arranged in a plurality of columns. A column in the IC is essentially a series of aligned circuit elements of the same type that extends from a first edge of the IC to a second edge. In addition there may be a center column having circuit elements of different types.

Abstract: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.