Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.

Abstract: A method of testing reliability in an integrated circuit including an array of test circuits, each test circuit including a resistor. The method includes selecting a first test circuit from the array, measuring a pre-stress resistance value for the resistor in the selected test circuit, applying a high stress current across the resistor, removing the high stress current, and measuring a post-stress resistance value for the resistor. Other embodiments include measuring additional resistance values before applying and after removing the high stress current. One embodiment includes applying a positive voltage to one stress input terminal, and then testing a short sensing terminal for the positive voltage, both before and after applying the high stress current. These steps test for whether or not the high stress current has created a short in the test circuit.

Abstract: A frequency synthesizer for a programmable logic device includes a phase alignment circuit that is controlled by an asynchronous level-mode state machine. The state machine receives a start signal generated by the circuits that determine a concurrence cycle when reference and generated clock signals should be aligned. Then, at the concurrence cycle the state machine replaces a generated clock edge with a reference clock edge to bring the generated clock signal into hard phase alignment with the reference clock signal.

Abstract: A pulse-width controller (1800) is described. Pulse generators (1700L, 1700H) are coupled to receive clock signals (1320, 1321) and configured to extend respective high-time and low-time pulse widths to provide signals with lengthened pulse widths (1320P, 1321P). Control signals (1803, 1804) are generated from pulse-width lengthened signals (1320P, 1321P). Clock signals (1320, 1321) and the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are provided to differential logic (1823 through 1828), such as Differential Cascode Voltage Switch Logic, to provide a differential output (1611, 1612) which is duty-cycle adjusted. The control signals (1803, 1804) in combination with the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are used to selectively activate a respective portion of the differential logic (1823 through 1828) to pass signals to the differential output (1611, 1612).

Abstract: Method and apparatus for testing a device embedded in a programmable logic device is described. Because an embedded device, such as a microprocessor core, comprises more input and output pins than a programmable logic device, such as a field programmable gate array, in which it is located, providing a test vector wider than the number of external input and output pins of the programmable logic device is problematic. To solve this problem, at least a portion of the programmable logic device is programmed to function as a vector controller, where a test vector may be provided to the vector controller in sections, reassembled by the vector controller and provided to the embedded device after reassembly. Moreover, a test vector result in response to the test vector input is obtained by the vector controller and sectioned for outputting.

Abstract: A level shifter for low voltage operation includes two level shifting stages. The first stage shifts the input voltage level to an intermediate voltage level, and the second stage shifts the intermediate voltage level to an output voltage level. This two-stage arrangement allows the level shifter to function for very low input voltages, and enables functionality across a wide range of output voltages. The first stage is designed to be compatible with very low input voltages and the intermediate voltage level is chosen to be within the safe operating limits of the first stage. The intermediate voltage level is also high enough to drive the high voltage devices of the second stage. This level shifter can be used where multiple output voltage levels are required depending on the particular application or operating mode.

Abstract: A method and system for time-stamping and managing electronic documents are described. A document manager obtains time-stamp certificates for the electronic documents. Document identifiers and associated certificate identifiers for the documents and certificates are used to build a database, and the documents and the certificates are stored for future reference.

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: An integrated circuit (I/C) assembly includes a dedicated voltage sensor line for determining with a high degree of accuracy the operating voltage at a predetermined sensor point on the IC die. The dedicated voltage sensor line connects the sensor point to an input/output (I/O) structure of the IC die, which in turn is connected to a voltage sense pin on the package of the IC assembly. In this manner, an end user can accurately monitor the operating voltage at the voltage sensor point on the IC. Additionally, an end user can connect a control circuit to the voltage sensor pin to control either the supply voltage or secondary parameters.

Abstract: A line driver with programmable slew rates is disclosed. The line driver can be configured to have a slew rate based on a desired fraction of the clock period of the system clock. Specifically, the clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay. A number of base delays is calculated to be equal to the desired fraction of the clock period multiplied by the clock period reference number. The slew rate of the line driver is adjusted to be equal to the number of base delays.

Abstract: Automatic tracking and assembly of changed portions of configuration data for partial run-time reconfiguration of a programmable logic device (PLD). The methods of an API that supports run-time reconfiguration applications for a PLD manage configuration data for partial reconfiguration. The API saves in application memory a copy of the configuration data used to configure the PLD. As the application updates selected portions of the in-memory configuration data, the API tracks which portions of the configuration data changed. When the application initiates reconfiguration of the PLD, the API partially reconfigures the PLD with the tracked changed portions of the configuration data. For readback of configuration data from the PLD, the API tracks which portions of in-memory configuration data are synchronized with the PLD.

Abstract: Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.

Abstract: A system and method are provided for replacing dedicated external termination resistors typically used to implement an asymmetrical unidirectional bus I/O standard with programmable resistances that are dynamically selected by programming output driver circuits having digitally controlled impedances.

Abstract: A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.

Abstract: A variety of CLB architectures enable the efficient implementation of sum-of-products functions in a PLD. Output signals from each lookup table (LUT) in a CLB are routed directly to a dedicated OR structure, bypassing other logic typically included in a CLB. Thus, the LUTs can be programmed to implement AND functions, with the AND function results being ORed together in the dedicated OR structure. In this manner, a fast and efficient sum-of-products output signal is provided. In some embodiments, the dedicated OR structure includes programmable means for selectively combining the signals from the LUTs. In these embodiments, LUTs with output signals that are ignored by the dedicated OR structure can be used to implement unrelated logic.

Abstract: Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.

Abstract: A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.