Abstract: Examples described herein provide a method for evaluating a programmable logic device (PLD) for compatibility with user designs. The method includes using a processor-based system: obtaining an indication of one or more failure bits of configuration memory of a programmable logic device (PLD); determining whether each of the one or more failure bits corresponds to a configuration memory bit to be used by a first PLD user design; if any of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as unusable for the first PLD user design; and if none of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as usable for the first PLD user design.

Abstract: An example preprocessor circuit includes: a first buffer configured to store rows of image data and output a row thereof; a second buffer, coupled to the first buffer, including storage locations to store respective image samples of the row output by the first buffer; shift registers; an interconnect network including connections, each connection coupling a respective one of the shift registers to more than one of the storage locations, one or more of the storage locations being coupled to more than one of the connections; and a control circuit configured to load the shift registers with the image samples based on the connections and shift the shift registers to output streams of image samples.

Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

Abstract: The present invention provides an antenna system (100, 200, 211, 300, 400, 500, 600) for attachment to an antenna pole (250, 350), the antenna system (100, 200, 211, 300, 400, 500, 600) comprising a cooling arrangement (101, 201, 212, 301, 401, 501, 601), an active electronic arrangement (102, 202, 213, 302, 402, 502, 602) that comprises a number of antenna elements (103, 104) and a number of receivers and/or transmitters for the antenna elements (103, 104), wherein the active electronic arrangement (102, 202, 213, 302, 402, 502, 602) is releasably attachable to the cooling arrangement (101, 201, 212, 301, 401, 501, 601). Further, the present invention provides a communication system (210) and a method for manufacturing an antenna system (100, 200, 211, 300, 400, 500, 600).

Abstract: Embodiments herein describe techniques for separating data transmitted between I/O functions in an integrated component and a host into separate data paths. In one embodiment, data packets are transmitted using a direct data path that bypasses a switch in the integrated component. In contrast, configuration packets (e.g., hot-swap, hot-add, hot-remove data, some types of descriptors, etc.) are transmitted to the switch which then forwards the configuration packets to their destination. The direct path for the data packets does not rely on switch connectivity (and its accompanying latency) to transport bandwidth sensitive traffic between the host and the I/O functions, and instead avoids (e.g., bypasses) the bandwidth, resource, store/forward, and latency properties of the switch. Meanwhile, the software compatibility attributes, such as hot plug attributes (which are not latency or bandwidth sensitive), continue to be supported by using the switch to provide a configuration data path.

Abstract: An integrated circuit (IC) device includes a network device including a first network port, a second network port, and an internal endpoint port. The IC device further includes a first processing unit including an internal end station. The first processing unit is configured to communicate with the network device using the internal endpoint port. The IC device further includes a second processing unit including a bridge management layer. The second processing unit is configured to communicate with the network device using the internal endpoint port. In various embodiments, the first processing unit and the second processing unit are configured to communicate with each other using a first internal channel.

Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

Abstract: A chip package assembly and method of fabricating the same are described herein. The chip package assembly generally includes at least one integrated circuit (IC) die that has had the original solder interconnects at least partially replaced to enhance the reliability of a redistribution layer disposed between the IC die and the substrate. In the resulting chip package assembly, at least one IC die includes first and second pillars extending from exposed contact pads through a first mold compound. The second pillars are fabricated from a material that has a composition different than that of the first pillars. A redistribution layer is formed on the first and second pillars. The solder interconnects mechanically couple the redistribution layer to landing pads of a substrate. The solder interconnects also electrically couple circuitry of the substrate to the circuitry of the IC die through the redistribution layer and first and second pillars.

Abstract: The disclosed approaches involve executing simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. Execution of each simulator-parallel process is initiated in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated by calling a first function of a wrapper from a first process of the simulator-parallel processes. The first process waits for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.

Abstract: A system can include a plurality of memory devices, wherein the plurality of memory devices includes at least three memory devices. The system can include an IC. The IC can include a memory controller coupled to each of the plurality of memory devices in parallel, wherein the memory controller is configured to broadcast a read command to each of the plurality of memory devices. The IC can include an error correction circuit coupled to each of the plurality of memory devices, wherein the error correction circuit is configured to compare data bits received from the plurality of memory devices responsive to the read command and output data bits corresponding to a majority of the data bits received from the plurality of memory devices. The IC can include a consumer circuit coupled to the error correction circuit, wherein the consumer circuit receives the data bits output from the error correction circuit.

Abstract: The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus, fine-grained allocation provides a flexible allocation of entries in a hardware cache that permits an administrator to reserve any number of entries for a particular tenant, but also permit other tenants to use this bandwidth when the reserved entries are not currently needed by the tenant.

Abstract: A data processing system comprising: a processing subsystem supporting a plurality of consumers, each consumer being arranged to process messages received into a corresponding receive queue; a network interface device supporting a virtual interface for each of the receive queues; and a hardware accelerator coupled to the processing subsystem by the network interface device and configured to parse one or more streams of data packets received from a network so as to, for each consumer: identify in the data packets messages having one or more of a set of characteristics associated with the consumer; and frame the identified messages in a new stream of data packets addressed to a network endpoint associated with the virtual interface of the consumer so as to cause said new stream of data packets to be delivered into the receive queue of the consumer.

Abstract: Embodiments herein describe a layer converter that includes a proxy legacy interface that permits the layers for a legacy interconnect protocol to be recycled without any modifications, thus achieving legacy functionality alongside the new protocols' layer implementation. Put differently, the layer converter permits the layers of the legacy interconnect protocol to be reused to permit data to be transmitted on a link shared with data transmitted using a new interconnect protocol.

Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.