Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

Abstract: Micro devices having enhanced through printed circuit board (PCB) heat transfer are provided. In one example, a micro device is provided that includes a PCB, a thermal management device, a chip package, a bracket, and a plurality of extra-package heat conductors. The chip package has a first side facing the thermal management device and a second side mounted to a first side of the PCB. The bracket is disposed on a second side of the PCB that faces away from the chip package. The plurality of extra-package heat conductors are disposed laterally outward of the chip package and provide at least a portion of a thermally conductive heat transfer path between the bracket and the thermal management device through the PCB.

Abstract: Disclosed approaches for converting between block coded format and raster format include buffers for first type component blocks and second type component blocks of a frame. The buffers are sized less than the width of the frame. A demultiplexer circuit is configured to input the first type component blocks and the second type component blocks in coded block order, and enable storage of the first type component blocks in the first buffer and of the second type component blocks in the second buffer in the coded block order. A multiplexer circuit is configured to flush data from the first buffer in raster scan order in response to a completed set of the first type component blocks in the first buffer, and flush data from the second buffer in raster scan order in response to a completed set of the second type component blocks in the second buffer.

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

Abstract: Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

Abstract: A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.

Abstract: Removing protections on a session-key protected design include receiving a double encrypted vendor private key and an encrypted session key. The double encrypted vendor private key is decrypted into a single encrypted vendor-private key using a user private key, and the single encrypted vendor-private key is decrypted into a vendor private key using a vendor pass phrase. The encrypted session key is decrypted into a session key using the vendor private key, and the session-key protected design is decrypted into a plain design using the session key.

Abstract: At least one neural network accelerator performs operations of a first subset of layers of a neural network on an input data set, generates an intermediate data set, and stores the intermediate data set in a shared memory queue in a shared memory. A first processor element of a host computer system provides input data to the neural network accelerator and signals the neural network accelerator to perform the operations of the first subset of layers of the neural network on the input data set. A second processor element of the host computer system reads the intermediate data set from the shared memory queue, performs operations of a second subset of layers of the neural network on the intermediate data set, and generates an output data set while the neural network accelerator is performing the operations of the first subset of layers of the neural network on another input data set.

Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

Abstract: A calibration system for calibrating a number of transceivers, each comprising an in-phase signal path and a quadrature signal path in receive direction and/or in transmit direction is disclosed herein.

Abstract: An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and configured to receive the differential residue voltage signal, and generate a first differential voltage signal from the differential residue voltage signal. The second amplifier includes second amplifier circuitry. The second amplifier is electrically connected to differential output nodes of the first amplifier, and configured to receive the first differential voltage signal, and generate a second differential voltage signal from the first differential voltage signal.

Abstract: Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H2, and a first data chunk C1. Signature S may be signed on a first hash H1. H1 may be the hash for H2 and C1. If signature S passes verification, a hash engine may perform hash functions on C1 and H2 to generate a hash H1?. H1? may be compared with H1 to indicate whether C1 has been tampered with or not. By using the incremental authentication, a signature that appears at the beginning of the image may be extended to the entire image while only using a small internal buffer. Advantageously, internal buffer may only need to store two hashes Hi, Hi+1, and a data chunk Ci, or, a signature S, a hash Hi, and a data chunk Ci.

Abstract: Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or system calls in the host program corresponding to the different functions then use jump logic to pass function selection values to an accelerator program in the accelerator that inform the accelerator program which function it is being instructed to perform. This jump logic can be generated by an accelerator compiler and then inserted into the host program as a host compiler generates the executable (e.g., the compiled binary) for the host program.

Abstract: The embodiments herein describe a conversion engine that converts floating point data into integer data using a dynamic scaling factor. To select the scaling factor, the conversion engine compares a default (or initial) scaling factor value to an exponent portion of the floating point value to determine a shift value with which to bit shift a mantissa of the floating point value. After bit shifting the mantissa, the conversion engine determines whether the shift value caused an overflow or an underflow and whether that overflow or underflow violates a predefined policy. If the policy is violated, the conversion engine adjusts the scaling factor and restarts the conversion process. In this manner, the conversion engine can adjust the scaling factor until identifying a scaling factor that converts all the floating point values in the batch without violating the policy.

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

Abstract: An example method of calibrating signals in an antenna array includes generating a calibration signal at a first radio sub unit (RSU), transmitting the calibration signal through a transmission path of a radio front end (RFE) of the first RSU, and receiving the calibration signal in a coupling and distribution layer of the first RSU. The method further includes providing the calibration signal from the coupling and distribution layer of the first RSU directly to a coupling and distribution layer of a second RSU, and processing the calibration signal at the second RSU.