Abstract: Methods and systems for invisible watermarking of images and video are disclosed. According to one embodiment, a method for watermarking video comprises selecting a block corresponding to a subset of pixels in a video frame. The block has quantized coefficients generated during encoding of the block. A modification function is applied to a candidate quantized coefficient (QC) in the block to incorporate a bit of a watermark message. The modification function is based on a set of configuration parameters.

Abstract: Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.

Abstract: Methods and systems for storing pixels of a video/image frame are disclosed. According to one embodiment, a method for storing pixels of a video frame comprises allocating a region of a memory to a pixel block having pixels of the video frame selected in out-of-raster-scan-order. The allocated region corresponds to a plurality of contiguous locations in the memory, and wherein the allocated region includes a first portion for storing pixel values. Values of pixels are stored in the pixel block in the first portion.

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

Abstract: An accelerator card can include a read-only memory configured to store a security identifier in a designated field therein and a satellite controller configured to read the security identifier in response to a reset event. The satellite controller is configured to select, based on the security identifier, a security mode from a plurality of security modes and implement the selected security mode in the accelerator card.

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

Abstract: An accelerator card can include a read-only memory configured to store a security identifier in a designated field therein and a satellite controller configured to read the security identifier in response to a reset event. The satellite controller is configured to select, based on the security identifier, a security mode from a plurality of security modes and implement the selected security mode in the accelerator card.

Abstract: An integrated circuit can include one or more clock controllers. Each clock controller corresponds to a different clock signal of a set of one or more clock signals of the integrated circuit. Each clock controller is configured to implement a clock stretch mode that generates a modified clock signal having a frequency that is less than the clock signal. The integrated circuit can include a trigger circuit configured to enable selected ones of the one or more clock controllers to implement the clock stretch mode. The trigger circuit and the one or more clock controllers are hardwired and are programmable using control infrastructure circuitry of the integrated circuit.

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

Abstract: A device includes a programmable passive measurement hardware engine, a programmable active measurement hardware engine, and a configuration engine. The programmable passive measurement hardware engine is configured to collect statistical data, from data transmission at a network line rate, used for network measurement. The programmable active measurement hardware engine is configured to generate probe packets and wherein the programmable active measurement hardware engine is further configured to collect responses to the generated probe packets, wherein the collected responses are used for the network measurement. The configuration engine is configured to receive data settings and wherein the configuration engine is further configured to program the programmable passive measurement hardware engine and the programmable active measurement hardware engine with the received data settings.

Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Abstract: Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of executable simulation models from the first storage location and then simulates the circuit design by executing the executable object and loading the executable simulation models in response to initiation by the executable object.

Abstract: Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable logic region. The interconnect is communicatively coupled to the control logic. The interconnect is operable to communicate the memory transaction request therethrough. The memory controller is communicatively coupled to the interconnect. The memory controller is operable to receive the memory transaction request. The memory controller is configurable to determine whether the memory transaction request is permitted based on the one or more transaction attributes.

Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.

Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.

Abstract: Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.