Abstract: A circuit and method for FPGAs to allow a user to supply a shutdown signal at an external pin which causes internal circuitry in the FPGA to turn off pass transistors in the word lines of every SRAM cell in the FPGA thereby preventing wasted power by current drain to ground through an SRAM cell that happens to be addressed when the FPGA is not being used.

Abstract: A core-based PLD programming method for programming a PLD to implement a user-defined logic operation including a set of cores. The PLD includes several configurable logic blocks (CLBs). Each core includes several logic portions that are arranged in a fixed pattern, and each logic portion includes configuration data for configuring one CLB. A placement process is performed during which only a single reference logic portion of each core is placed in a configuration data table to form a first placement pattern. Non-reference portions of the cores are not placed in the configuration data table during the initial placement process. An annealing process is then performed during which the reference logic portions associated with the cores are moved between CLB sites in an attempt to identify an optimal placement solution. A separate CLB site overlap table is utilized to keep track of the non-reference logic portions during the annealing process.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the body effect loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its body effect voltage loss.

Abstract: An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer.

Abstract: The present invention provides an apparatus for converting logic signals of a first voltage level to logic signals of a second voltage level in response to a control signal indicative of whether logic signals on an associated target device are of the first or second voltage level. An output configuration includes a de-multiplexer having an input terminal coupled to receive an output signal of an associated logic circuit, a control terminal coupled to receive a control signal, and first and second output terminals, the first de-multiplexer output terminal being connected to the target device. A switch coupled between the second de-multiplexer output terminal and the target device has a control terminal coupled to receive the control signal. When the control signal is in a first state, a voltage drop across the switch converts the logic signals of the first voltage level to logic signals of the second voltage level.

Abstract: An array of memory cells including a first block of memory cells having a first replacement column of memory cells is provided. The first replacement column is able to replace any defective column of memory cells in the first block. To accomplish this, a defective column in the first block is identified. A first set of data (intended for the defective column) is stored in the first replacement column. The first set of data is then routed from the first replacement column to output terminals of the defective column using a set of bit lines in the first block. The array can further include a second block of memory cells having a second replacement column of memory cells, along with a set of switches for selectively connecting and disconnecting bit lines in the first and second blocks. The set of switches provides a means to divide the bit lines into separate bit lines for the first and second blocks, thereby allowing defective columns in the first and second blocks to be repaired simultaneously.

Abstract: A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Abstract: A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.

Abstract: A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Abstract: A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large non-field programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moreover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array.

Abstract: A post-placement residual overlap removal process for use with core-based programmable logic device programming methods that is called when an optimal placement solution includes one or more overlapping cores. Horizontal and vertical constraint graphs are utilized to mathematically define the two-dimensional positional relationship between the cores of the infeasible placement solution in two separate one-dimensional (i.e., horizontal and vertical) directions. Next, the constraint graphs are analyzed to determine whether they include a feasible solution (i.e., whether the overlaps existing in the placement solution can be removed simply by reallocating available resources to the overlapping cores). If one of the constraint graphs is not feasible, then the infeasible constraint graph is revised, and then the feasibility of both graphs is re-analyzed for feasibility. The feasibility analysis and constraint graph revision steps are repeated until both constraint graphs are feasible.

Abstract: A method of computer aided design of coarse grain FPGA's by employing a library of selected primitive cells, defining the connection classes useful in the FPGA design, and assigning appropriate connection classes to the inputs and outputs of the respective primitive cells. The primitive cells and defined interconnections used therein have accurately established timing and power parameters thereby enabling more accurate assessments of static timing and power consumption for the entire FPGA design. Moreover, the method of the present invention results in placement directives which then serve as connection criteria in carrying out subsequent place and route algorithms. One such placement directive is implemented as a "local output" (LO) of some of the primitive cells which implies that that particular output must be connected to another primitive cell input within the local configurable logic block (CLB). Another such placement directive is obtained by using a plurality of virtual buffers.

Abstract: A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.

Abstract: The invention provides a method for implementing an HDL-specified priority encoder as carry logic in an FPGA. A first embodiment of the method includes the steps of: 1) detecting an priority determination statement in the HDL code; 2) implementing the highest priority test in the statement using a first carry multiplexer; and 3) implementing the next highest priority test in the statement using another carry multiplexer that accepts the output of the preceding carry multiplexer as a carry input; and 4) repeating step 3 until each test in the statement has been implemented. Another embodiment of the invention includes the additional steps of: 1) counting the number of tests performed in the priority determination statement; and 2) comparing the number of tests to a set threshold criterion, to determine whether it is appropriate to implement the statement using carry logic.

Abstract: A system and method for altering the effective operating frequency of an electronic system (e.g., an IC) in response to changes in temperature or current provides controlled and deliberate performance degradation. Reducing the effective operating frequency at high temperatures allows an IC to maintain a relatively stable power consumption. A first embodiment of the invention includes a temperature transducer, an Analog-to-Digital (A/D) converter, a select generator, and a clock frequency divider. The temperature transducer measures the temperature, which is converted by the A/D converter to a digital value. The digital temperature value drives the select generator, which generates one or more select signals. The select signals control the clock frequency divider to produce a clock signal with an effective clock frequency that depends on the measured temperature. According to a second embodiment of the invention, a current transducer is used instead of a temperature transducer.

Abstract: A power-on reset circuit is provided which uses a dual voltage detection circuit to output a voltage detection signal. The dual voltage detection circuit is coupled to a first supply voltage terminal, a second supply voltage terminal, and a ground terminal. The voltage detection signal indicates whether the first supply voltage provided on the first supply voltage terminal is greater than an adequate voltage level. Furthermore, the voltage detection signal is driven by circuits powered by a second supply voltage provided on the second supply voltage terminal. One embodiment of the dual-voltage detection circuit comprises a first transistor coupled in series with a second transistor between the first supply voltage terminal and the ground terminal, as well as a third transistor coupled in series with a fourth transistor between the second supply voltage terminal and the ground terminal.

Abstract: Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.

Abstract: A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

Abstract: A method and apparatus for generating circuitry to initialize memory contained in an integrated circuit generated from a description for a programmable logic device is provided. The initialization bits in the bit stream used to program the programmable logic device are identified and extracted. Using these initialization bits and a set of selectable control circuitry options, initialization control logic is generated. Data initialization logic is also generated using the extracted initialization bits.

Abstract: A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.