Abstract: The invention provides a technique for generating a portable software class that includes native methods, i.e., a software class compatible with interpreters conforming to two or more different interfaces. Therefore, the method of the invention allows the development of code that simultaneously supports two or more native method interfaces. The portable software class references a plurality of interface libraries, each of which interfaces to native methods included in the class. While in any given situation all but one of the interface libraries are unused, the overhead of carrying these extra libraries is minimal. The interface libraries are preferably generated from a shared piece of user-generated code. According to another embodiment of the invention, a separate version of the user-generated interface code is generated for each interface library.

Abstract: A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.

Abstract: A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided.

Abstract: An FPGA configured for computation of an N.times.N discrete Fourier transform (DFT) using polynomial transforms defined in modified rings of transforms, comprising a first buffer for ordering a set of polynomial data in a two dimensional matrix, a multiplier for multiplying each element of the two dimensional matrix by .omega..sup.-n.sbsp.2 (where .omega.=e.sup.-j.pi./N, e is a constant (ln(e)=1),j=.sqroot.-1, n.sub.2 =the column index number in the matrix, and N=the transform length) to produce a premultiplication product, a polynomial transform circuit for performing a polynomial transform (PT) modulo (z.sup.N +1), size N, root z.sup.2 on the premultiplication product to produce a polynomial transform result, where z represents the unit delay operator, a reduced DFT calculator for performing N reduced DFTs of N terms on the polynomial transform result to produce a permuted output, and an address generator for reordering the permuted output to a natural order.

Abstract: An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer.

Abstract: A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics. The direct connections of the invention are the preferred interconnect path between logic blocks because they substantially reduce the average interconnect delay, thereby allowing the programmable logic device to operate at a higher speed.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: A method is provided for scan testing that eliminates the need for balancing internal scan clock delays. According to the method of the invention, multiple scan clocks are provided, each being provided to a different set of flip-flops. The skew between the active edges of the scan clocks is deliberately increased to the point where each set of flip-flops has plenty of time to settle before the next set of flip-flops receives a clock pulse. Because scan testing is typically performed at clock speeds of only about 1 Megahertz, there is time for each of the scan clocks to pulse separately from all the others, without increasing the test time. The increased delay between scan clock pulses eliminates the need for balancing internal delays on the scan clock paths, thereby greatly reducing the number of placement and routing iterations required to achieve a functional design.

Abstract: A programmable logic device (PLD) includes a fixed EXCLUSIVE OR gate and a programmable logic array (PLA). The PLA includes a plurality of AND gate and a plurality of OR gates, the output of each AND gate being programmably connected to an input of each of the plurality of OR gates. The output of one of the OR gates of the PLA array is fed to one of the inputs of the fixed EXCLUSIVE OR. Since the output of each of the AND gates is available to each of the OR gates in the PLA array, implementation of the EXCLUSIVE OR function is facilitated and the number of product terms (AND gates) required is reduced as compared to known PLDs. The output of a programmable array logic (PAL) array having a plurality of AND gates non-programmably connected to an OR gate is connected to the other one of the inputs of the fixed EXCLUSIVE OR gate.

Abstract: A method is described for measuring localized operating temperatures and voltages on an integrated circuit. The integrated circuit includes an oscillator circuit with a frequency that varies with temperature and/or applied voltage. The frequency of the oscillator is then determined, using a constant voltage, for a number of temperatures to establish a known relationship between oscillation frequency and temperature. Once the relationship is known, a similar oscillator is included within or adjacent a second circuit of the integrated circuit. The operating temperature or operating voltage of the second circuit may then be determined by monitoring the frequency of the oscillator while the second circuit is operational.

Abstract: A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length.

Abstract: A variable clock divider circuit is provided. The variable clock divider circuit receives an input clock signal and generates an output clock signal having an output clock frequency that is less than the input clock frequency of the input clock signal. In one embodiment, a controller generates a rising-edge control signal and a falling-edge control signal. An output generator drives rising edges on the output clock signal in response to active edges on the rising-edge control signal. Conversely, the output generator drives falling edges on the output clock signal in response to active edges on the falling-edge control signal. The frequency of the rising-edge control signal and the frequency of the falling-edge control signal are variable. Common settings for the frequency of the rising-edge control signal and the falling-edge control signal include the frequency of the input clock signal divided by an integer.

Abstract: A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a corresponding cell access transistor. A row access circuit is coupled to the row lines. To re-program a first set (but not a second set) of configuration memory cells in a column, the row access circuit initially pre-charges each of the row lines, and then provides configuration data values on a first set (but not a second set) of the row lines. All cell access transistors in the column are coupled to a column select line. To avoid losing data in any memory cell, a relatively low read voltage, followed by a higher write voltage, is applied to the column select line. When the read voltage is applied to the column select line, the associated cell access transistors are weakly turned on.

Abstract: An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

Abstract: A user-defined logic device, such as a field programmable gate array (FPGA), having a dedicated internal bus, a plurality of dedicated bus interface circuits, and a programmable logic array. The dedicated bus interface circuits are connected in parallel to the dedicated internal bus. The programmable logic array is programmable to implement one or more functions. The programmable logic array is coupled to the dedicated bus interface circuits, such that each function is coupled to a corresponding bus interface circuit. The functions can communicate with one another through the bus interface circuits and internal bus, or through communication pathways located within the programmable logic array. In addition, the functions can communicate with devices external to the user-defined logic device through a bus bridge circuit which is coupled to the dedicated internal bus, or directly through the pins of the user-defined logic device.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: A method for controlling the operation of an FPGA. Initially, a function generator of the FPGA is configured as a ROM look up table which holds a first set of data values. These data values are selectively routed to an output terminal of the function generator in response to a plurality of input signals which are provided to the function generator. The first set of data values is selected to define a first function implemented by the function generator. Subsequently, the function generator is reconfigured as a user RAM, thereby enabling a second set of data values to be written to the function generator. The function generator is then reconfigured as a ROM look up table which holds the second set of data values. These data values are selectively routed to the output terminal of the function generator in response to the input signals provided the function generator. The second set of data values is selected to define a second function implemented by the function generator.

Abstract: The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a six-input-function multiplexer or function generator. The six-input-function multiplexer or function generator therefore produces an output that can be any function of up to six inputs. Some functions of up to nineteen inputs can also be generated in a single CLE.

Abstract: An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the FPGA. On power-on or reset, the non-volatile memory configures a first portion of the FPGA using configuration data stored in the non-volatile memory. Other portions of the FPGA can also be configured using the embedded non-volatile memory. Alternatively, an external configuration device can configure the other portions of the FPGA through a configuration port. Further, either the embedded non-volatile memory or the external configuration device can reconfigure the first portion of the FPGA.

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.