Abstract: A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to another with no external memory access, thereby transferring data to/from the storage elements in the logic plane at very high speed. Typically, all the local memory can be simultaneously transferred to/from other memory planes in one cycle. Each FPGA configuration provides a virtual instruction. The present invention uses two different types of virtual instructions: computational and pattern manipulation instructions. Computational instructions perform some computation with data stored in some pre-defined local memory pattern. Pattern manipulation instructions move the local data into different memory locations to create the pattern required by the next instruction.

Abstract: A field programmable gate array (FPGA) having an array of configurable logic blocks (CLBs) which can be partially reconfigured. Each column of CLBs is connected to a corresponding column select line, and each row of CLBs is connected to a corresponding row select line. A rectangular set of CLBs to be reconfigured is selected, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs. Column select signals are asserted on the column select lines associated with the one or more consecutive columns of CLBs. Similarly, row select signals are asserted on the row select lines associated with the one or more consecutive rows of CLBs. CLBs which receive both an asserted column select signal and an asserted row select signal are enabled for reconfiguration.

Abstract: The present invention provides a novel clock frequency divider that accepts an input clock having an input clock frequency and provides an output clock with an effective clock frequency of one of 1/N, 2/N, . . . , (N-1)/N, N/N times the input clock frequency, where N is an integer. The clock frequency divider of the present invention divides the input clock frequency asymmetrically by filtering out one or more of each N pulses on the input clock, as dictated by select signals. For example, in a clock frequency divider having N=8, a first clock output signal filters out one of each eight pulses, retaining seven pulses. Therefore, the effective frequency of the output clock signal is (N-1)/N, or 7/8, times the frequency of input clock signal. Similarly, a second output clock signal retains six of every eight pulses, a third retains five, and so forth.

Abstract: The invention provides a structure and method for configuring an FPGA from a PROM using a boundary scan chain. A PROM is provided that comprises JTAG circuitry. Configuration data is stored in the PROM memory as in known PROMs. When the data is retrieved from the PROM memory it is provided on a standard JTAG Test Access Port (TAP). The JTAG-compatible PROM is included as part of a JTAG scan chain, preferably directly preceding the FPGA to be configured by the PROM. The PROM can be controlled either externally or via JTAG commands received down the scan chain. Therefore, a reconfiguration of the FPGA can be initiated via standard JTAG commands. In one embodiment, the PROM itself is programmed with the FPGA configuration data using the JTAG TAP port.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A method for using shared signal lines for interconnection of logic elements and configuration of a programmable gate array. A signal line which is shared for purposes of interconnection and configuration saves chip space. During configuration, a shared signal line is used to route configuration bits to configuration memory cells, and during operation of the programmable gate array, the shared signal line is used to interconnect logic elements of the programmable gate array.

Abstract: A method for controlling power consumption and output slew rate in a programmable logic device, which is programmable to emulate a user-defined logic function. After placing and routing the user-defined logic function such that a plurality of paths are assigned to associated resources of the programmable logic device, a group of the resources associated with at least one path of the logic function which is constrained by a user-defined timing specification is identified. These resources are sorted according to their respective power consumption. A first sub-group of the resources is then identified which, when operated in a low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of all paths.

Abstract: Treatment of the positive electrode interface of an antifuse provides significantly improved on-state reliability. Treatments include, but are not limited to, a plasma etch using carbon tetrafluoride (CF.sub.4), a sputter clean using Argon, and wet chemical treatments using dimethyl formamide (and water) or a resist developer.

Abstract: The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate.

Abstract: An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.

Abstract: A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or automatically selected and applied during implementation of a placement algorithm.

Abstract: Described are delay circuits that are relatively insensitive to changes in temperature and supply voltage. A delay circuit includes at least one inverter circuit made up of a pair of transistors. The inverter responds to voltage changes on the input terminal by providing corresponding inverse changes on the output terminal. The speed at which the inverter responds to voltage changes on the input terminal depends upon the ability of one or both transistors to conduct current to or from the output terminal. The ability of one or both transistors in the inverter to move charge to or from the output terminal is restricted to reduce the switching speed of the inverter, thus imposing a delay on the input signal. Further, the restricted current is provided at a reference level that is relatively insensitive to temperature changes and supply-voltage fluctuations.

Abstract: A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.

Abstract: A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of the FPGA as a decoder. Encoded configuration data is transferred to the decoder, which then configures other portions of the FPGA. In one embodiment, the decoder is a decompression unit, which decompresses compressed configuration data. In another embodiment, the decoder is an interpreter, which interprets configuration commands. In some embodiments, the portion of the FPGA used for the decoder can be reconfigured after the configuration of the other portions of the FPGA.

Abstract: A chip includes a programmable logic device and a microprocessor, wherein at least one of the associated registers of the microprocessor is distributed in the programmable logic device. The distributed register is coupled to both the microprocessor and the programmable logic device. In this manner, the microprocessor has the ability to access the register and place a value into the programmable logic device all in one clock cycle. Additionally, the logic functions in the programmable logic device are also advantageously available to the microprocessor.

Abstract: A flash reconfigurable programmable logic device is applied as a dynamic execution unit for a sequence of instructions. The sequence of instructions includes control portion, and a portion which indicates which configuration of the flash configurable programmable logic device is to be used with that instruction. In each execution cycle, a configuration is selected in accordance with the instruction being executed, switching from one configuration of the programmable logic device to any other configuration stored on the device in a single cycle. The configuration store stores a set of configuration words defining respective logic functions of the configurable logic elements in the programmable logic device. The configuration select circuits operate to apply a selected configuration word from the set of configuration words to configure the configurable logic elements. An instruction store stores a sequence of instructions for execution by the programmable logic device.

Abstract: A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer.

Abstract: The invention provides a multiplexer structure having an efficient quadrilateral layout. The multiplexer structure includes a first multiplexer and a second multiplexer, both being coupled to receive a plurality of common input signals. Each multiplexer has a first stage and a second stage. The first stages of the first and second multiplexers are fabricated in a plurality of adjacent multiplexer stripes. Each multiplexer stripe includes a plurality of interleaved pass transistors. The multiplexer stripes are fabricated in parallel with each other along a first axis. Gate electrodes of the pass transistors extend in parallel with each other along a second axis that is perpendicular to the first axis. One or more rows of memory cells extend along the second axis, adjacent to the multiplexer stripes. These memory cells control the pass transistors in the multiplexer stripes.

Abstract: A configurable logic block (CLB) which includes a function generator, carry logic and a first multiplexer. To operate the CLB as a multiplier, the function generator and the carry logic are each coupled to receive a first multiplier bit, a second multiplier bit and a carry signal. The function generator and carry logic are configured to provide a sum signal and a carry signal, respectively, in response to these input signals. The first multiplexer is coupled to receive the sum signal, the first multiplier bit, the second multiplier bit and a logic zero signal. The first multiplexer is controlled to pass a selected one of these signals in response to a first multiplicand bit and a second multiplicand bit. As a result, the CLB effectively creates and adds the partial products which result from multiplying the first and second multiplier bits and the first and second multiplicand bits.